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US 6,636,095 B2Granted
Semiconductor integrated circuit device
AssigneeHitachi, Ltd.
InventorsYusuke Nitta, Toshihiro Hattori
Life of this patent
Estimating the term…
Abstract
A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equalized in length in the form of a tree structure, and clock lines connecting lower stage clock drivers are made as short as possible.
Claims4
A semiconductor integrated circuit device comprising:
- a plurality of logic blocks, each logic block including a plurality of flip-flops, wherein none of the plurality of logic blocks includes both a plurality of first flip-flops arranged in a first area with a first plurality of stages of clock drivers furnished on first clock lines ranging from a first root clock driver to the plurality of first flip-flops and a plurality of second flip-flops arranged in a second area with a second plurality of stages of clock drivers furnished on second clock tines ranging from a second root clock driver to the plurality of second flip-flops.
Dependencies are inferred from the claim text.