Compensation for a delay locked loop

A delay line of a delay locked loop, the delay line comprising:

• a plurality of directly coupled delay elements;
• a minimum delay boundary adjacent to a first end of the delay line and a maximum delay boundary adjacent to a second end of the delay line;
• and
• at least one delay element adjacent to the maximum delay boundary and operably coupled to the plurality of delay elements through at least one multiplexer.

A delay locked loop comprising:

• a plurality of directly coupled delay elements having a maximum delay element and a minimum delay element at each end;
• first circuitry configured to select at least one delay element from among any of the plurality of delay elements;
• and
• second circuitry configured to preclude the first circuitry from selecting at least one of the maximum delay element and the minimum delay element from among the plurality of delay elements.

A delay locked loop comprising:

• a plurality of directly coupled delay elements;
• first circuitry configured to select at least one delay element from among the plurality of delay elements;
• and
• second circuitry configured to preclude the first circuitry from selecting at least one other delay element operably coupled to the plurality of delay elements, wherein the second circuitry comprises at least one multiplexer responsive to at least one control signal.

A delay locked loop comprising:

• a plurality of directly coupled delay elements;
• first circuitry configured to select at least one delay element from among the plurality of delay elements;
• and
• second circuitry configured to preclude the first circuitry from selecting at least one other delay element operably coupled to the plurality of delay elements, wherein the second circuitry is further configured to allow the at least one other delay element to be selected in response to an indication from phase comparator circuitry associated with the second circuitry that a delay signal is substantially in phase with a reference signal.

An electronic circuit including at least one delay line of a delay locked loop comprising:

• a plurality of directly coupled delay elements;
• a minimum delay boundary adjacent a first delay element of the plurality of delay elements and a maximum delay boundary adjacent a second delay element of the plurality of delay elements;
• at least one delay element adjacent to the minimum delay boundary and operably coupled to the plurality of delay elements through at least one multiplexer;
• and
• at least one other delay element adjacent to the maximum delay boundary and operably coupled to the plurality of delay elements through at least one other multiplexer.

An electronic circuit including at least one delay line of a delay locked loop comprising:

• a plurality of directly coupled delay elements;
• a minimum delay boundary adjacent to a first end of the at least one delay line and a maximum delay boundary adjacent to a second end of the at least one delay line;
• and
• at least one delay element adjacent to the maximum delay boundary and operably coupled to the plurality of delay elements through at least one multiplexer.

An electronic system comprising:

• a processor;
• and
• at least one of an input device, an output device and a data storage device associated with the processor;
• wherein at least one component of the electronic system comprises:
• a plurality of delay elements directly coupled as a delay line of a delay locked loop, the plurality of delay elements having a maximum delay element and a minimum delay element at each end;
• first circuitry configured to select at least one delay element from among any of the plurality of delay elements;
• and
• second circuitry configured to preclude the first circuitry from selecting at least one of the maximum delay element and the minimum delay element from among the plurality of delay elements.

An electronic system comprising:

• a processor;
• and
• at least one of an input device, an output device and a data storage device associated with the processor;
• wherein at least one component of the electronic system comprises:
• a plurality of delay elements directly coupled as a delay line of a delay locked loop;
• first circuitry configured to select at least one delay element from among the plurality of delay elements;
• and
• second circuitry configured to preclude the first circuitry from selecting at least one other delay element operably coupled to the plurality of delay elements, wherein the second circuitry comprises at least one multiplexer responsive to at least one control signal.

An electronic system comprising:

• a processor;
• and
• at least one of an input device, an output device and a data storage device associated with the processor;
• wherein at least one component of the electronic system comprises:
• a plurality of delay elements directly coupled as a delay line of a delay locked loop;
• first circuitry configured to select at least one delay element from among the plurality of delay elements;
• and
• second circuitry configured to preclude the first circuitry from selecting at least one other delay element operably coupled to the plurality of delay elements, wherein the second circuitry is further configured to allow the at least one other delay element to be selected in response to an indication from phase comparator circuitry associated with the second circuitry that a delay signal is substantially in phase with a reference signal.

A semiconductor wafer including circuitry fabricated thereon, the circuitry comprising:

• a plurality of delay elements directly coupled as a delay line of a delay locked loop;
• a minimum delay boundary adjacent a first delay element of the plurality of delay elements and a maximum delay boundary adjacent a second delay element of the plurality of delay elements;
• at least one delay element adjacent to the minimum delay boundary and operably coupled to the plurality of delay elements through at least one multiplexer;
• and
• at least one other delay element adjacent to the maximum delay boundary and operably coupled to the plurality of delay elements through at least one other multiplexer.

A method of initializing a delay locked loop, the method comprising:

• receiving an initialization signal;
• establishing at least one artificial boundary on a delay line of the delay locked loop;
• and
• selecting a delay setting for the delay locked loop within the at least one artificial boundary.