Spike current reducing circuit

Abstract

Charge accumulated at an output node of an output transistor is discharged to the ground through the output transistor as a spike current. To reduce noise of the spike current, a control signal is sent from an output transistor driving circuit set to a low impedance to the output transistor in a first driving stage to quickly turn on the output transistor, a control signal is sent from the output transistor driving circuit set to a high impedance to the output transistor in a second driving stage to output the spike current through the output transistor at a fixed rate, and a control signal is sent from the output transistor driving circuit set to a low impedance to the output transistor in a third driving stage to quickly discharge all the charge. Therefore, a time-current characteristic of the spike current is set almost in a trapezoid shape, and both a spike current peak value and a spike current occurrence time period in the spike current can be sufficiently lowered.

Dependencies are inferred from the claim text.