Apparatus for detecting edges of input signal to execute signal processing on the basis of edge timings
AssigneeNEC Electronics Corporation
InventorMasaaki Soda
Life of this patent
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Abstract
An apparatus for detecting an edge timing of an input signal and operating on the basis of the edge timing while power consumption thereof is reduced. The apparatus includes an edge detecting circuit that detects edges of an input signal to generate an edge timing representing signal representative of edge timings of the edges, a signal processing circuit responsive to the edge timing representing signal. The edge detection circuit outputs an enable signal to enable the signal processing circuit to operate when the edge detection circuit finds one of the edges. The signal processing circuit executes a signal processing of the edge timing representing signal in response to the enable signal.
Claims13
An apparatus comprising:
- an edge detecting circuit which detects edges of a non return to zero (NRZ) input signal to generate an edge timing representing signal representative of edge timings of said edges;
- a signal processing circuit responsive to said edge timing representing signal, wherein
- said edge detecting circuit outputs an enable signal to enable said signal processing circuit to operate when said edge detecting circuit finds one of said edges;
- said signal processing circuit executes a signal processing of said edge timing representing signal in response to said enable signal.
A clock signal reproducing circuit comprising:
- an edge detecting circuit which detects edges of a non return to zero (NRZ) input signal to generate an edge timing representing signal representative of edge timings of said edges;
- a clock signal outputting circuit responsive to said edge timing representing signal for generating another clock signal synchronized with said input signal, wherein
- said edge detecting circuit outputs an enable signal to enable said clock signal outputting circuit to operate when said edge detecting circuit finds one of said edges.
A signal reproducing circuit comprising:
- an edge detecting circuit which detects edges of a non return to zero (NRZ) input signal to generate an edge timing representing signal representative of edge timings of said edges;
- a clock signal outputting circuit responsive to said edge timing representing signal for generating another clock signal synchronized with said input signal;
- and
- a reproduced signal outputting circuit sampling said input signal with said another clock signal to output a reproduced signal, wherein
- said edge detecting circuit outputs an enable signal to enable said clock signal outputting circuit to operate when said edge detecting circuit finds on of said edges.
A signal reproducing circuit comprising:
- detecting edges of a non return to zero (NRZ) input signal;
- outputting an edge timing representing signal representative of edge timings of said edges;
- outputting an enable signal when one of said edges is detected;
- and
- enabling a circuit to operate in response to said edge timing representing signal.
Dependencies are inferred from the claim text.