US 6,636,074 B2 · Clock gating to reduce power consumption of control and status registers

Abstract

Various systems and methods for reducing the power consumption of CSRs (Control and Status Registers) within an integrated circuit (IC) are disclosed. In one embodiment, an IC includes a plurality of CSRs. Each CSR includes one or more flip-flops that are used to store one or more bits of control and/or status information for an associated device on the IC. The IC also includes one or more clock gates. Each clock gate is coupled to provide a gated clock signal to one or more of the flip-flops in a respective one of the CSRs. Each clock gate is configured to output a clock signal as the gated clock signal if a clock enable signal that corresponds to the respective CSR is asserted. The IC also includes one or more clock gating units that are each configured to generate the clock enable signal for a respective one of the CSRs.

Claims9

Dependent claims

An integrated circuit comprising:

a plurality of CSRs (Control and Status Registers), wherein each CSR includes one or more flip-flops;
one or more clock gates, wherein each clock gate is coupled to provide a gated clock signal to one or more of the flip-flops in a respective one of the CSRs, wherein each clock gate is configured to output a clock signal as the gated clock signal if a clock enable signal that corresponds to the respective CSR is asserted;
and
one or more clock gating units, wherein each clock gating unit is configured to generate the clock enable signal for the respective one of the plurality of CSRs, wherein a first clock gating unit is configured to assert the clock enable signal for a first one of the CSRs in response to detecting a software update to the first CSR.

1 more element

Dependencies are inferred from the claim text.

Clock gating to reduce power consumption of control and status registers

Life of this patent

Clock gating to reduce power consumption of control and status registers

Life of this patent

Abstract

Claims9