Transmitting circuit, receiving circuit, transmitting-receiving circuit and electro-optical apparatus
AssigneeSeiko Epson Corporation
InventorSatoshi Yatabe
Life of this patent
Estimating the term…
Abstract
A circuit for transmitting/receiving a logic signal through a capacitor is provided, which prevents signal delay and malfunction on the receiving circuit side. The power supply voltage of the buffer that transmits the logic signal in the transmitting circuit is enhanced to be larger than the power supply voltage of the buffer that inputs the logic signal in the receiving circuit. As a result, the amplitude of the logic signal at the input point is expanded from the clipping level according to the protection diodes, so that the signal delay, as well as the malfunction are prevented.
Claims18
A receiving circuit that receives a logic signal transmitted from a transmitting circuit through a capacitor, said receiving circuit comprising:
- a logic element to which received logic signal is input, a power supply voltage to the logic element to which the received logic signal is input being made smaller than an amplitude voltage of a logic signal transmitted from said transmitting circuit;
- a buffer that inputs the received logic signal;
- and
- a feedback circuit that feeds back an output signal of said buffer to an input of said buffer.
A receiving circuit that receives a logic signal transmitted from a transmitting circuit through a capacitor, said receiving circuit comprising:
- a logic element to which received logic signal is input, a power supply voltage to the logic element to which the received logic signal is input being made smaller than an amplitude voltage of a logic signal transmitted from said transmitting circuit;
- and
- a buffer that buffers by adding a hysteresis characteristic to the received logic signal.
A transmitting-receiving circuit, comprising:
- a transmitting circuit that transmits a logic signal;
- a receiving circuit that receives the logic signal transmitted from said transmitting circuit through a capacitor, an amplitude voltage of the logic signal transmitted from said transmitting circuit being larger than a power supply voltage to a logic signal that receives said logic signal in said receiving circuit;
- and
- two sets of power supply voltages with approximately equal voltage differences being alternately supplied for a predetermined period of time as a power supply voltage to the logic element that receives the logic signal.
A transmitting buffer, in a controlling circuit, that transmits to a receiving buffer, in a driving circuit that drives an electro-optical element under the control of the controlling circuit, through a connection line therebetween having a wiring resistance and a stray capacitance, a logic signal relevant to the driving of the electro-optical element having an amplitude voltage that is larger than a power supply voltage of the receiving buffer and that is sufficiently large-to reduce a delay time of the logic signal due to the wiring resistance and the stray capacitance of the connection line so that the delay time is shorter than the duration of the logic signal.
A transmitting buffer that transmits to a receiving buffer, through a connection line therebetween having a wiring resistance and a stray capacitance, a logic signal having an amplitude voltage that is larger than a power supply voltage of the receiving buffer and that is sufficiently large to reduce a delay time of the logic signal due to the wiring resistance and the stray capacitance of the connection line so that the delay time is shorter than the duration of the logic signal.
A receiving buffer, in a driving circuit that drives an electro-optical element, that receives a logic signal relevant to the driving of the electro-optical element through a connection line therebetween having a wiring resistance and a stray capacitance, from a transmitting buffer in a controlling circuit that controls the driving of the driving circuit, wherein the logic signal has an amplitude voltage that is larger than a power supply voltage of the receiving buffer and that is sufficiently large to reduce a delay time of the logic signal due to the wiring resistance and the stray capacitance of the connection line so that the delay time is shorter than the duration of the logic signal.
A receiving buffer that receives from a transmitting buffer, through a connection line therebetween having a wiring resistance and a stray capacitance, a logic signal having an amplitude voltage that is larger than a power supply voltage of the receiving buffer and that is sufficiently large to reduce a delay time of the logic signal due to wiring resistance and the stray capacitance of the connection line so that the delay time is shorter than the duration of the logic signal.
Dependencies are inferred from the claim text.