Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

An integrated circuit in a semiconductor die comprising:

• an external communications terminal including a supply voltage bond pad;
• an internal memory circuit;
• switching circuitry coupled between the external communications terminal and the internal memory circuit for selectively isolating the internal memory circuit from the external communications terminal in response to receiving a control signal;
• and
• control circuitry coupled to the external communications terminal and the switching circuitry for sensing a short in the internal memory circuit and outputting the control signal to the switching circuitry in response thereto, the control circuitry comprising:
• a first PMOS transistor having a source coupled to a supply terminal, a gate coupled to an output terminal, and a drain coupled to a control signal terminal;
• a first resistive device coupled between the supply terminal and the output terminal;
• a second resistive device coupled between the control signal terminal and a reference voltage bond pad;
• a second PMOS transistor having a source coupled to the supply terminal, a gate, and a drain coupled to the control signal terminal;
• an inverter coupled between the control signal terminal and the gate of the second PMOS transistor;
• and
• circuitry for sensing a voltage applied to the internal memory circuit.

A semiconductor wafer having a plurality of integrated circuits in a plurality of semiconductor dice on the semiconductor wafer, each integrated circuit of the plurality of integrated circuits comprising:

• an external communications terminal for connecting to a supply voltage;
• an internal memory circuit;
• switching circuitry coupled between the external communications terminal and the internal memory circuit for selectively isolating the internal memory circuit from the external communications terminal in response to receiving a control signal;
• and
• control circuitry coupled to the external communications terminal and the switching circuitry for sensing a short in the internal memory circuit and outputting the control signal to the switching circuitry in response thereto, the control circuitry comprising:
• a first PMOS transistor having a source coupled to a supply terminal, a gate coupled to an output terminal, and a drain coupled to a control signal terminal;
• a first resistor coupled between the supply terminal and the output terminal;
• a second resistor coupled between the control signal terminal and a reference voltage bond pad;
• a second PMOS transistor having a source coupled to the supply terminal, a gate, and a drain coupled to the control signal terminal;
• an inverter coupled between the control signal terminal and the gate of the second PMOS transistor;
• and
• circuitry for sensing a voltage applied to the internal circuit.

A method for isolating and testing integrated circuits in each of a plurality of semiconductor dice on a semiconductor wafer, the method comprising:

• providing control circuitry within each semiconductor die of the plurality of semiconductor dice for sensing a short in an integrated circuit in each of the plurality of semiconductor dice, the control circuitry comprising:
• a first PMOS transistor having a source coupled to a supply terminal, a gate coupled to an output terminal, and a drain coupled to a control signal terminal;
• a first resistive device coupled between the supply terminal and the output terminal;
• a second resistive device coupled between the control signal terminal and a reference voltage bond pad;
• a second PMOS transistor having a source coupled to the supply terminal, a gate, and a drain coupled to the control signal terminal;
• an inverter coupled between the control signal terminal and the gate of the second PMOS transistor;
• circuitry for sensing a voltage applied to the internal circuit;
• and
• testing the plurality of semiconductor dice so that when the control circuitry in one of the plurality of semiconductor dice senses a short, automatically switching and isolating an integrated circuit having the short in the one of the plurality of semiconductor dice from other integrated circuits in the plurality of semiconductor dice.

A method for isolating a short-circuiting integrated circuit of a semiconductor die of a semiconductor wafer from another semiconductor die formed on the semiconductor wafer interconnected with the short-circuiting integrated circuit of the semiconductor die, the method comprising:

• sensing the short-circuiting integrated circuit of the semiconductor die using control circuitry, the control circuitry comprising:
• a first PMOS transistor having a source coupled to a supply terminal, a gate coupled to an output terminal, and a drain coupled to a control signal terminal;
• a first resistive device coupled between the supply terminal and the output terminal;
• a second resistive device coupled between the control signal terminal and a reference voltage bond pad;
• a second PMOS transistor having a source coupled to the supply terminal, a gate, and a drain coupled to the control signal terminal;
• an inverter coupled between the control signal terminal and the gate of the second PMOS transistor;
• circuitry for sensing a voltage applied to the internal circuit;
• and
• in response thereto, automatically switching and isolating the short-circuiting integrated circuit of the semiconductor die from another semiconductor die.

In an integrated circuit of a semiconductor die of a wafer, the integrated circuit having an internal circuit, the internal circuit having a reference voltage bond pad and an external terminal for communication between the internal circuit and circuitry external to the integrated circuit, a device for isolating the internal circuit from the external terminal for communication, the device comprising:

• control circuitry for sensing a short in the internal circuit and outputting a control signal in response thereto, the control circuitry including a supply voltage terminal coupled to the external terminal for receiving a supply voltage, the external terminal comprising a supply voltage bond pad for receiving the supply voltage, an output terminal for outputting the supply voltage, and a control signal terminal for outputting the control signal in response to a current flow between the supply voltage terminal and the output terminal exceeding a predetermined threshold, said control circuitry including:
• a first PMOS transistor having a source coupled to the supply voltage terminal, a gate coupled to the output terminal, and a drain coupled to the control signal terminal;
• a first resistor coupled between the supply voltage terminal and the output terminal;
• a second resistor coupled between the control signal terminal and a reference voltage bond pad;
• a second PMOS transistor having a source coupled to the supply voltage terminal, a gate, and a drain coupled to the control signal terminal;
• an inverter coupled between the control signal terminal and the gate of the second PMOS transistor;
• circuitry for sensing a voltage applied to the internal circuit;
• and
• switching circuitry coupled to the control circuitry for isolating the internal circuit from the external terminal for communication in response to receiving the control signal.