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US 6,636,067 B1Granted
Method of testing for micro latch-up
AssigneeTexas Instruments Incorporated
InventorJorge Salcedo-Suner
Life of this patent
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Abstract
A reliable method of testing a CMOS-based integrated circuit device having a low-impedance path between I/O pin(s) and GND for potential micro-latch-up. The test method detects a low impedance path between the integrated circuit device I/O pin(s) and GND(s) caused by a parasitic SCR that is not detectable using conventional latch-up detection test methods.
Claims7
A method of testing a CMOS based integrated circuit device, the method comprising the steps of:
- applying a maximum supply voltage to at least one first input pin;
- measuring a first supply current from the at least one first input pin;
- applying a strike pulse to a second input pin that is adjacent to at least one first input pin;
- measuring a second supply current from the at least one first input pin subsequent to conclusion of the strike pulse to the second input pin;
- and
- comparing the first supply current with the second supply current to determine whether a micro-latch-up condition is present.
3 more elements
A micro-latch-up test circuit comprising:
- a CMOS-based integrated circuit device having a supply pin, a ground pin, a plurality of input pins, and at least one output pin;
- a power supply operational to deliver a maximum supply voltage to the supply pin and at least one input pin selected from the plurality of input pins;
- a first current measurement instrument operational to measure supply current from the at least one input pin selected from the plurality of input pins;
- a second current measurement instrument operational to measure supply current from the supply pin;
- and
- a trigger pulse current source operational to deliver a strike pulse to a device input pin adjacent the at least one input pin receiving the maximum supply voltage, wherein each output pin is left unconnected.
3 more elements
Dependencies are inferred from the claim text.