Semiconductor integrated circuit and method for testing the same

A method for testing a semiconductor integrated circuit, comprising the steps of:

• providing a semiconductor integrated circuit comprising a plurality of output buffers each comprising a P-channel transistor and an N-channel transistor, the P-channel transistor in its drain and the N-channel transistor in its drain having been commonly bonded to an external output terminal;
• selecting one output buffer from the plurality of output buffers;
• bringing the P-channel transistor and the N-channel transistor provided in the selected one of said output buffers to an ON state connecting a gate of the P-channel transistor in the selected one of said output buffers to a first source of a first constant voltage at which the P-channel transistor operates in an unsaturated region;
• and connecting a gate of the N-channel transistor in the selected one of said output buffers to a second source of a second constant voltage at which the N-channel transistor operates in an unsaturated region;
• bringing the P-channel transistor and the N-channel transistor provided in the remaining output buffers to an OFF state and bringing external output terminals of the remaining output buffers to a high-impedance state;
• allowing a current to flow into the P-channel transistor and the N-channel transistor, which have been brought to an ON state, to measure the resistance values of the P-channel transistor and the N-channel transistor.