Semiconductor package with a chip connected to a wiring substrate using bump electrodes and underfilled with sealing resin

A semiconductor device comprising:

• a semiconductor chip which has a first surface and a second surface opposite to the first surface;
• a plurality of bump electrodes formed on the first surface of the semiconductor chip;
• a wiring substrate which has a first surface and a second surface opposite to the first surface, wherein said first surface of the wiring substrate is connected to the semiconductor chip by the bump electrodes;
• and
• a sealing resin filled between the semiconductor chip and the wiring substrate,
• wherein said second surface of the semiconductor chip and said second surface of the wiring substrate are exposed from the sealing resin,
• wherein a peripheral edge of the semiconductor chip and a peripheral edge of the wiring substrate are aligned, and
• wherein the sealing resin has a scribed surface which is aligned with the peripheral edge of the semiconductor chip and the peripheral edge of the wiring substrate.

A semiconductor device comprising:

• a semiconductor chip which has a first surface and a second surface opposite to the first surface;
• a plurality of bump electrodes formed on the first surface of the semiconductor chip;
• a wiring substrate which has a first surface and a second surface opposite to the first surface, wherein said first surface of the wiring substrate is connected to the semiconductor chip by the bump electrodes;
• and
• a sealing resin which seals between the semiconductor chip and the wiring substrate including a peripheral portion of the first surface of the semiconductor chip and a peripheral portion of the first surface of the wiring substrate, wherein said second surface of the semiconductor chip and said second surface of the wiring substrate are exposed from the sealing resin,
• wherein the sealing resin has a first surface which is aligned with said second surface of the semiconductor chip and has a second surface that is aligned with said second surface of the wiring substrate.