Semiconductor device with trench isolation structure
AssigneeMacronix International Co., Ltd.
InventorsHan-Chao Lai, Hung-Sui Lin, Tao-Cheng Lu
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Abstract
A semiconductor device with trench isolation structure is disclosed. The invention uses a trench isolation structure that can be formed by using conventional methods to prevent problems such as drain induced barrier lowering (DIBL), punch-through leakage and spiking leakage. Thus these poor electrical properties of the conventional semiconductor device with a shallow junction depth resulting from the shrink of design rules can be solved.
Claims20
A semiconductor device with a trench isolation structure, said semiconductor device comprising:
- a substrate having a trench isolation structure, a source region and a drain region therein, wherein said trench isolation structure isolates and is between said source and said drain region;
- a crystalline silicon layer on said trench isolation structure, said source and said drain region;
- a gate oxide layer on a portion of said crystalline silicon layer which is on said trench isolation structure;
- and
- a gate electrode directly on said gate oxide layer.
A semiconductor device with a trench isolation structure, said semiconductor device comprising:
- a substrate having a trench isolation structure, a source region and a drain region therein, wherein said trench isolation structure isolates and is between said source and said drain region;
- a crystalline silicon layer on said trench isolation structure, said source and said drain region having a lightly doped drain region therein;
- a gate oxide layer on a portion of said crystalline silicon layer which is on said trench isolation structure;
- and
- a gate electrode directly on said gate oxide layer, wherein said gate electrode has a spacer adjacent the sidewall of said gate electrode.
A semiconductor device with a trench isolation structure, said semiconductor device comprising:
- a substrate having a trench isolation, a source region and a drain region therein, wherein said trench isolation structure isolates and is between said source and said drain region;
- an in situ doped epitaxial silicon layer on said trench isolation structure, said source and said drain region;
- a gate oxide layer on a portion of said in situ doped epitaxial silicon layer which is on said trench isolation structure;
- and
- a gate electrode directly on said gate oxide layer, wherein said gate electrode has a spacer adjacent the sidewall of said gate electrode.
Dependencies are inferred from the claim text.