Semiconductor integrated circuit device operating with low power consumption
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHideto Hidaka
Life of this patent
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Abstract
Transistors having large gate tunnel barriers are used as transistors to be on in a standby state, MIS transistors having thin gate insulating films are used as transistors to be off in the standby state, and main and sub-power supply lines and main and sub-ground lines forming a hierarchical power supply structure are isolated from each other in the standby state so that a gate tunnel current is reduced in the standby state in which a low power consumption is required. In general, a gate tunnel current reducing mechanism is provided for any circuitry operating in a standby state and an active state, and is activated in the standby state to reduce the gate tunnel current in the circuitry in the standby state, to reduce power consumption in the standby state.
Claims5
A semiconductor device having a standby cycle and an active cycle and receiving an input signal of a predetermined logical level in said standby cycle, comprising:
- a first insulated gate field effect transistor connected between a first power source node and a first output node, receiving said input signal on a gate thereof, and having a first tunnel barrier;
- and
- a second insulated gate field effect transistor connected between said first output node and a sub-power source node, receiving said input signal on a gate thereof, and rendered conductive complementarily to said first insulated gate field effect transistor, said second insulated gate field effect transistor having a second gate tunnel barrier smaller than said first gate tunnel barrier;
- and
- a first switching transistor connected between said sub-power supply node and a second power source node, and selectively rendered conductive in response to an operation cycle instructing signal.
Dependencies are inferred from the claim text.