DRAM capacitor formulation using a double-sided electrode
AssigneeMicron Technology, Inc.
InventorsScott J. DeBoer, Husam Al-Shareef, Randhir Thakur
Life of this patent
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Abstract
A capacitor having a double sided electrode for enhanced capacitance. In one embodiment, the double sided electrode capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The double sided electrode is preferably formed of a conductive metal, provided that an oxide of the metal is conductive. The double sided electrode capacitor provides a capacitor that has high storage capacitance which provides an increased efficiency for a cell without an increase in the size of the cell.
Claims20
A method of forming a memory cell comprising the steps of
- forming a transistor including a source and a dram over an active area of a substrate, wherein said source of said transistor is connected to a bit line and a gate of said transistor is connected to a word line;
- and
- forming a capacitor connected to said drain of said transistor and to a voltage reference, wherein said step of forming said capacitor further comprises
- forming a first conductive layer as a double sided electrode having an inner side and an outer side, said outer side being adjacent to at least one insulating layer;
- forming a first dielectric layer over the inner side of the double sided electrode;
- exposing at least a portion of the at least one insulating layer on the outer sided electrode to form an exposed portion of said double sided electrode;
- forming a second dielectric layer over said first dielectric layer and said exposed portion of said double sided electrode;
- and
- forming a second conductive layer over said second dielectric layer.
A method of forming a pair of memory cells connected to a common bit line, said method comprising the steps of:
- forming respective transistors corresponding to said pair of memory cells, each of said respective transistors including a source and a drain over an active area of a substrate, wherein said source of each of said respective transistors is connected to a bit line and a gate of each of said respective transistors is connected to a word line;
- and
- forming respective capacitors corresponding to said respective transistors, wherein each of said respective capacitors is connected to said drain of each of said respective transistors and to a voltage reverence, wherein said step of forming each of said respective capacitors further comprises
- forming a first conductive layer as a double sided electrode having an inner side and an outer side, said outer side being adjacent to at least one insulating layer;
- forming a first dielectric layer over the inner side of the double sided electrode;
- exposing at least a portion of the at least one insulating layer on the outer side of said first conductive layer to form an exposed portion of said double sided electrode;
- forming a second dielectric layer over said first dielectric layer and said exposed portion of said double sided electrode;
- and
- forming a second conductive layer over said second dielectric layer.
Dependencies are inferred from the claim text.