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US 6,635,546 B1Granted
Method and manufacturing MRAM offset cells in a damascene structure
AssigneeInfineon Technologies AG
InventorX. J. Ning
Life of this patent
Estimating the term…
Abstract
A method of manufacturing an offset MRAM device (110), including utilizing two resist layers either to pattern a magnetic stack layer to form offset conductive lines (158) and magnetic memory cells (160), or to pattern an insulating layer to form vias (168) to expose magnetic memory cells and trenches (170) for conductive lines, or both, using a single etch process.
Claims21
A method of manufacturing a resistive semiconductor memory device, comprising:
- forming a plurality of first conductive lines;
- depositing a first insulating layer over the first conductive lines;
- patterning the first insulating layer with vias to expose at least some of the first conductive lines;
- depositing a magnetic stack layer over the first insulating layer and exposed first conductive lines;
- patterning the magnetic stack layer to form magnetic memory cells and offset conductive lines adapted to couple the exposed first conductive lines to the magnetic memory cells;
- depositing a second insulating layer over the magnetic memory cells and offset conductive lines;
- forming vias to expose at least some of the magnetic memory cells and forming trenches for conductive lines within the second insulating layer;
- and
- filling the vias and trenches within the second insulating layer with a conductive material, wherein at least one of patterning the magnetic stack layer to form magnetic memory cells and offset conductive lines or forming vias to expose at least some of the magnetic memory cells and forming trenches for conductive lines win the second insulating layer comprise a single etch process.
6 more elements
A method of manufacturing a magnetic random access memory (MRAM) device, comprising:
- providing a workpiece;
- depositing a first insulating layer over the workpiece;
- forming a plurality of first conductive lines within the first insulating layer;
- depositing a second insulating layer over the first conductive lines;
- patterning the second insulating layer with vias to expose at least some of the first conductive lines;
- depositing a magnetic stack layer over the second insulating layer and exposed first conductive lines;
- depositing a first resist over the magnetic stack layer;
- patterning and developing the first resist;
- removing portions of the first resist;
- depositing a second resist over the magnetic stack layer and first resist;
- patterning the second resist;
- etching the magnetic stack layer in a single etch process to form magnetic memory cells and offset conductive lines adapted to couple the exposed first conductive lines to the magnetic memory cells;
- depositing a third insulating layer over the magnetic memory cells and offset conductive lines;
- forming vias to expose at least some of the magnetic memory cells and forming trenches for conductive lines within the third insulating layer;
- and
- filling the vias and trenches within the third insulating layer with a conductive material.
13 more elements
A method of manufacturing a magnetic random access memory (MRAM) device, comprising:
- providing a workpiece;
- depositing a first insulating layer over the workpiece;
- forming a plurality of first conductive lines within the first insulating layer;
- depositing a second insulating layer over the first conductive lines;
- patterning the second insulating layer with vias to expose at least some of the first conductive lines;
- depositing a magnetic stack layer over the second insulating layer and exposed first conductive lines;
- patterning the magnetic stack layer to form magnetic memory cells and offset conductive lines adapted to couple the exposed first conductive lines to the magnetic memory cells;
- depositing a third insulating layer over the magnetic memory cells and offset conductive lines;
- depositing a first resist over the third insulating layer;
- patterning and developing the first resist;
- removing portions of the first resist;
- depositing a second resist over the third insulating layer and the first resist;
- patterning the second resist;
- etching the third insulating layer in a single etch process to form vias to expose at least some of the magnetic memory cells and forming trenches for conductive lines within the third insulating layer;
- and
- filling the vias and trenches within the third insulating layer with a conductive material.
13 more elements
Dependencies are inferred from the claim text.