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US 6,635,542 B2Granted
Compact body for silicon-on-insulator transistors requiring no additional layout area
AssigneeInternational Business Machines Corporation
InventorsJeffrey W. Sleight, John J. Ellis-Monaghan, Suk Hoon Ku, Patrick R. Varekamp
Life of this patent
Estimating the term…
Abstract
A non-critical block mask exposes one of the source and drain in an SOI FET, which is implanted with a leakage implant that increases the leakage in the exposed element, thus providing a conductive path to draw away holes from the transistor body.
Claims9
A method of forming an SOI integrated circuit comprising the steps of:
- preparing an SOI substrate having a silicon device layer above an underlying dielectric, including forming a set of isolation members that define a set of active areas in said device layer;
- forming a set of NFETs in said set of active areas, said set of NFETs having a set of NFET sources, a set of NFET gates and a set of NFET drains;
- forming a block mask that exposes said set of NFET sources of said set of NFETs while blocking said set of NFET drains;
- implanting a set of p-n source junctions at said set of NFET sources with a leakage implant to form body contacts from portions of said silicon device layer below said set of NFET gates through said p-n source junctions to said NFET sources;
- and
- completing said SOI integrated circuit.
3 more elements
A method for forming an SOI integrated circuit comprising the steps of:
- preparing an SOI substrate having a silicon device layer above an underlying buried dielectric layer, including forming a set of isolation members that define a set of active areas in said device layer;
- forming a set of NFETs in said set of active areas, said set of NFETs having a set of NFET sources, a set of NFET gates and a set of NFET drains;
- forming a block mask that exposes said set of NFET sources of said set of NFETs while blocking said set of NFET drains;
- implanting a set of p-n source junctions at said set of NFET sources with a leakage implant that forms a body contact having a conductive path from that portion of said device layer below said set of NFET gates through said set of p-n source junctions to said set of sources;
- and
- completing said SOI integrated circuit.
3 more elements
A method of forming an SOI integrated circuit comprising the steps of:
- preparing an SOI substrate having a silicon device layer above an underlying buried dielectric layer, including forming a set of isolation members that define a set of active areas in said device layer;
- forming a set of NFETs in said set of active areas, said set of NFETs having a set of NFET sources, a set of NFET gates and a set of NFET drains;
- forming a set of PFETs in said set of active areas, said set of PFETs having a set of PFET drains, a set of PFET gates and a set of PFET sources;
- forming a block mask that a) exposes said set of NFET sources of said set of NFETs while blocking said set of NFET drains;
- and b) exposes said set of PFET drains of said set of PFETs while blocking said set of PFET sources;
- implanting a set of p-n source junctions at said set of NFET sources and a set of p-n drain junctions at said set of PFET drains with a leakage implant that forms body contacts having conductive paths from that portion of said device layer below said sets of NFET gates through said set of p-n source junctions to said set of NFET sources and from that portion of said device layer below said sets of PFET gates through said set of p-n drain junctions to said set of PFET drains;
- and
- completing said SOI integrated circuit.
5 more elements
Dependencies are inferred from the claim text.