US 6,635,538 B2Granted

Method of manufacturing a semiconductor device

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsToshinori Morihara, Yoshinori Tanaka

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Abstract

When sidewalls (10) are formed by anisotropic etching, an insulating film (9) serves as a protective film for a major surface of a semiconductor substrate (100) and therefore prevents the major surface from suffering etching damage. That relieves an electric field concentration in a pn junction, to effectively take advantage of an LDD structure. Since a portion of the insulating film (9) extending off the sidewalls (10) is removed, there is no need for etching of the insulating film (9) when the contact holes (12) are formed and only an insulating film (11) is etched. That prevents a short circuit between main electrodes (13) and a gate electrode (7) and makes it possible to determine the spacing between the contact holes (12) narrower than the width of the gate electrode (7).

A method of manufacturing a semiconductor device, comprising the steps of:

(a) preparing a semiconductor substrate having a major surface of a first conductivity type;
(b) forming a first insulating film on said major surface;
(c) forming a gate electrode on said first insulating film;
(d) selectively introducing an impurity into said major surface with said gate electrode as a mask to selectively form a pair of low-concentration semiconductor layers in said major surface that are separated from each other with at least a portion of a region immediately below said gate electrode interposed therebetween;
(e) forming a second insulating film for covering said gate electrode and said first insulating film at least after said step (c);
(f) depositing a material whose main component is different from that of said second insulating film so as to entirely cover an exposed surface above said major surface after said steps (d) and (e);
(g) anisotropically etching said material deposited in said step (f) to form sidewalls for covering sides of said gate electrode and a portion of said first insulating film adjacent to said gate electrode;
(h) performing a selective etching to selectively remove a portion of said second second insulating film existing along said first insulating film and uncovered by said sidewalls;
(i) selectively introducing an impurity into said major surface with said gate electrode, said second insulating film, and said sidewalls as a mask to selectively form a pair of high-concentration semiconductor layers of a second conductivity type having opposed edges recessed from opposed edges of said pair of low-concentration semiconductor layers, being deeper and higher in concentration than said pair of low-concentration semiconductor layers, in said major surface at least after said step (g);
and
(j) connecting a pair of main electrodes to said pair of high-concentration semiconductor layers, respectively,
wherein said sidewall formed in step (g) remains after step (j) is carried out.

9 more elements

Facts

Application

09/866,708Filed 30 May 2001 · division

Priority

JP P10-32189712 Nov 1998

Published

US 2001/0028088 A111 Oct 2001

Granted

21 Oct 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10D 1/692
Capacitors having no potential barriers: electrodes
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 64/021
Manufacture or treatment: using multiple gate spacer layers, e.g. bilayered sidewall spacers

Abstract

Claims4