Method of planarizing a conductive plug situated under a ferroelectric capacitor

A method of fabricating a planar conductive via in an opening through a dielectric layer having a top surface, a bottom surface and the opening having sides, said method comprising the steps of:

• depositing a first conductive material on said top surface of said dielectric layer and in said opening in said dielectric layer to substantially fill said opening with said conductive material;
• removing the portion of said first conductive material located on said dielectric layer;
• depositing, by chemical vapor deposition, a first barrier layer over the remaining first conductive material in the opening, the first barrier layer extending over the top surface of said dielectric layer;
• then forming a second barrier layer over the first barrier Layer, the second barrier layer acting as a diffusion barrier to prevent oxidation of said first conductive material and extending over the top surface of the dielectric layer;
• depositing a bottom electrode layer over the second barrier layer;
• depositing a layer of a ferroelectric capacitor dielectric material over the bottom electrode layer;
• depositing a top electrode layer over the layer of ferroelectric capacitor dielectric material;
• and
• then etching the top electrode layer, layer of ferroelectric capacitor dielectric material, bottom electrode layer, and the second barrier layer, to define a capacitor at a location overlying the first conductive material in the opening.