Structure and method for dual work function logic devices in vertical DRAM process
AssigneeInfineon Technologies AG
InventorsRajeev Malik, Rama Divakaruni, Rajesh Rengarajan
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Abstract
Dual work function transistors are provided in a cmos support area 14 with an embedded vertical dram array 12. A wordline layer 54, and nitride cap layer 56 cover the dram array 12 and a gate oxide layer 42 and an undoped polysilicon layer 44 cover the support area 14. A common mask is applied and patterned over the substrate to define the wordlines line structures in the dram array 12 and the gate structures in the support 14. The unwanted portions of the layers 54, 56, 42 and 44 are removed by etching.
Claims20
A method for forming wordlines in a memory array area and dual function logic gates in a support area on a semiconductor substrate including the steps of:
- forming vertical dram cells in the array area of the substrate;
- depositing a layer of undoped polysilicon over the surface of the substrate;
- removing the undoped polysilicon from over the memory array;
- depositing a layer of wordline material over the surface of the substrate;
- removing the wordline material from over the logic devices;
- applying a gate mask to the surface of the substrate;
- using the same gate masks applied in the prior step, selectively removing portions of the unmasked wordline material and portions of the unmasked undoped polysilicon to form wordlines for the memory array and gates for the logic array.
Dependencies are inferred from the claim text.