CMOS-type semiconductor device and method of fabricating the same

A method of fabricating a semiconductor device including a plurality of CMOS transistors each of which comprises p- and n-type thin film transistors and which are classified into at least two element groups having different operating voltages, said method comprising the steps of:

• non-selectively doping a thin film with p-type impurities, said thin film to be an active semiconductor layer including first prospective regions to form p-type thin film transistors and second prospective regions to form n-type thin film transistors;
• selectively doping only said second prospective regions of said thin film with p-type impurities at a higher concentration than that in said step of non-selectively doping;
• annealing said thin film to activate the p-type impurities contained therein;
• forming an insulating film on at least a portion of said prospective regions for forming said p- and n-type thin film transistors after said non-selective doping step or said selective doping step;
• and
• forming element structures in said thin film after said steps of non-selectively and selectively doping, each of said structures including a gate electrode and source/drain regions which is separated from said gate electrode by said insulating film,
• wherein each of said element groups is subjected to a predetermined number of times of said step of non-selectively doping necessary for the element group and a predetermined number of times of said step of selectively doping necessary for the element group so that threshold voltages of the p- and n-type thin film transistors constituting the element group are independently set in accordance with the operating voltage of the element group.

A method of fabricating a semiconductor device including a plurality of CMOS transistors each of which comprises p- and n-type thin film transistors and which are classified into at least two element groups having different operating voltages, said method comprising the steps of:

• non-selectively doping a thin film with p-type impurities, said thin film to be an active semiconductor layer including first prospective regions to form p-type thin film transistors and second prospective regions to form n-type thin film transistors;
• selectively doping only said second prospective regions of said thin film with p-type impurities at a higher concentration than that in said step of non-selectively doping;
• annealing said thin film to activate the p-type impurities contained therein;
• forming an insulating film on at least a portion of said prospective regions for forming said p- and n-type thin film transistors after said non-selective doping step or said selective doping step;
• and
• forming element structures in said thin film after said non-selective step or said selective doping step, each of said structures including a gate electrode and source/drain regions which is separated from said gate electrode by said insulating film,
• wherein each of part of said element groups is subjected to a predetermined number of times of said step of non-selectively doping necessary for the element group and a predetermined number of times of said step of selectively doping necessary for the element group, and each of the other part of said element groups is subjected to only a predetermined number of times of said step of non-selectively doping necessary for the element group, so that threshold voltages of the p- and n-type thin film transistors constituting each of said element groups are independently set in accordance with the operating voltage of the element group.