Computer-readable storage media stored with a delay library for designing a semiconductor integrated circuit device
AssigneeHitachi, Ltd.
InventorsPeter Maurice Lee, Goichi Yokomizo
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Abstract
The invention relates to a design system of logic products, which includes a time-consuming detailed simulation part and a fast whole-product simulation part. Two new parameters Ac and n are added to a delay library of the fast whole-product simulation part for the purpose of hot carrier degradation calculations (Degradation=Actn) (wherein n is a slope of time dependence and depends on a bias voltage that the circuit configuration and cells receive, and Ac depends on the bias voltage that the circuit configuration and cells receive). Thereby, it is feasible to carry out optimization of the design by a fast whole-product simulation part without crossing the time-consuming detailed simulation part.
Claims13
A computer-readable storage medium stored with a delay library of at least one logic cell constituting at least a part of a logic product, said delay library including:
- at least one input signal transition time applicable to said logic cell;
- at least one output capacitance applicable to said logic cell;
- at least one hot carrier degradation parameter corresponding to said input signal transition time and said output capacitance, said parameter being determined by a transient bias voltage to be applied to said logic cell and a circuit configuration of said logic cell;
- and
- a degradation simulation function calculating an age dependent change of a delay time of said logic cell being expressed as an exponential function of said hot carrier degradation parameter with a simulated age of said logic cell as a base when said input signal transition time and said output capacitance are applied to said logic cell.
A computer-readable storage medium stored with a delay library of logic cells constituting a semiconductor integrated circuit device, wherein said delay library including:
- a critical path of said semiconductor integrated circuit device composed of some of said logical cells;
- a plurality of input signal transition times applicable to said logic cells;
- a plurality of output capacitances applicable to said logic cells;
- at least one hot carrier degradation parameter corresponding to one of said input signal transition time and one of said output capacitance, said parameter being determined by a transient bias voltage to be applied to a corresponding logic cell and a circuit configuration of said logic cell;
- and
- a degradation simulation function for calculating an age dependent change of a delay time of said logic cell being expressed as an exponential function of said hot carrier degradation parameter with a simulated age of said logic cell as a base, when one of said plurality of input signal transition times and one of said plurality of output capacitances are given said logic cell.
Dependencies are inferred from the claim text.