Delay/load estimation for use in integrated circuit design
AssigneeLSI Logic Corporation
InventorsGrant Lindberg, Stefan Graef
Life of this patent
Estimating the term…
Abstract
Delay and/or load estimation is performed prior to physical layout in an integrated circuit (IC) design process. Initially, a description of the IC design is obtained, the description being in a hardware description language (HDL). Floor planning is then performed based on the HDL description, and buffers are inserted into the IC design based on such floor planning. Finally, delays and/or loads are estimated in the IC design while taking into account the effect of the buffers. The buffers are inserted in the foregoing processing based on anticipated processing later in the IC design process.
Claims20
A method for performing delay estimation prior to physical layout in an integrated circuit (IC) design process, said method comprising:
- (a) obtaining a description of the IC design in a hardware description language (HDL);
- (b) performing floor planning based on the HDL description;
- (c) inserting buffers into the IC design based on said floor planning;
- and
- (d) estimating delays in the IC design while taking into account effects of the buffers,
- wherein the buffers are inserted in step (c) based on anticipated processing later in the IC design process.
A method for performing load estimation prior to physical layout in an integrated circuit (IC) design process, said method comprising:
- (a) obtaining a description of the IC design in a hardware description language (HDL);
- (b) performing floor planning based on the HDL description;
- (c) inserting buffers into the IC design based on said floor planning;
- and
- (d) estimating loads in the IC design while taking into account effects of the buffers,
- wherein the buffers are inserted in step (c) based on anticipated processing later in the IC design process.
A computer-readable medium storing computer-executable process steps for performing delay estimation prior to physical layout in an integrated circuit (IC) design process, said process steps comprising steps to:
- (a) obtain a description of the IC design in a hardware description language (HDL);
- (b) perform floor planning based on the HDL description;
- (c) insert buffers into the IC design based on said floor planning;
- and
- (d) estimate delays in the IC design while taking into account effects of the buffers,
- wherein the buffers are inserted in step (c) based on anticipated processing later in the IC design process.
An apparatus for performing delay estimation prior to physical layout in an integrated circuit (IC) design process, said apparatus comprising:
- (a) means for obtaining a description of the IC design in a hardware description language (HDL);
- (b) means for performing floor planning based on the HDL description;
- (c) means for inserting buffers into the IC design based on said floor planning;
- and
- (d) means for estimating delays in the IC design while taking into account effects of the buffers,
- wherein the buffers are inserted in step (c) based on anticipated processing later in the IC design process.
A computer-readable medium storing computer-executable process steps for performing load estimation prior to physical layout in an integrated circuit (IC) design process, said process steps comprising steps to:
- (a) obtain a description of the IC design in a hardware description language (HDL);
- (b) perform floor planning based on the HDL description;
- (c) insert buffers into the IC design based on said floor planning;
- and
- (d) estimate loads in the IC design while taking into account effects of the buffers,
- wherein the buffers are inserted in step (c) based on anticipated processing later in the IC design process.
An apparatus for performing load estimation prior to physical layout in an integrated circuit (IC) design process, said apparatus comprising:
- (a) means for obtaining a description of the IC design in a hardware description language (HDL);
- (b) means for performing floor planning based on the HDL description;
- (c) means for inserting buffers into the IC design based on said floor planning;
- and
- (d) means for estimating loads in the IC design while taking into account effects of the buffers,
- wherein the buffers are inserted in step (c) based on anticipated processing later in the IC design process.
Dependencies are inferred from the claim text.