Design verification by symbolic simulation using a native hardware description language
AssigneeInnologic Systems, Inc.
InventorsJohn Xiaoxiong Zhong, Dian Yang, Zheng Zhou, Ting Wang
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Abstract
A method and apparatus for performing design verification is described. In one embodiment, a method for performing design verification includes specifying at least one object that represents at least one signal as a symbol in a design using a first command and instructing a symbolic simulator with the first command to treat the at least one object as a symbol.
Claims18
A method for performing design verification, the method comprising:
- specifying at least one description language object that represents at least one signal as a symbol in a design using a first statement that is part of a description language, wherein the first statement comprises a Programming Language Interface (PLI) statement;
- and
- instructing a symbolic simulator in response to the first statement to treat the at least one description language object as a symbol.
An article of manufacture having at least one recordable medium having stored thereon executable instructions which, when executed by at least one processing device, cause the at least one processing device to:
- specify at least one description language object that represents at least one signal as a symbol in a design using a first statement that is part of a design language, wherein the first statement comprises a Programming Language Interface (PLI) statement;
- and
- instruct a symbolic simulator in response to the first statement to treat the at least one description language object as a symbol.
Dependencies are inferred from the claim text.