Test circuit of semiconductor memory

A test circuit of a semiconductor memory, comprising:

• internal clock enabling signal producing means for producing an internal clock enabling signal set to a first level from a first write recovery test signal set to the first level and an external clock enabling signal, of which a phase is shifted from that of an external clock signal by ½L (L is a positive integer higher than 1) of a pulse repetition period of the external clock signal or which is set to a second level;
• internal clock signal producing means for producing an internal clock signal, of which a pulse repetition period is 1/N (N is a positive integer, and N=L for the positive integer higher than 1) of the pulse repetition period of the external clock signal, from the internal clock enabling signal produced by the internal clock enabling signal producing means, the external clock signal, the first write recovery test signal set to the first level and the external clock enabling signal;
• internal write command signal and internal pre-charge signal producing means for producing an internal write command signal and a first pre-charge signal, of which a leading edge is shifted from that of the internal write command signal by ½ N of the pulse repetition period of the external clock signal, from the internal clock signal produced by the internal clock signal producing means, an external write command signal set to the second level, the first write recovery test signal set to the first level and the external clock signal;
• and
• a first selector for outputting the first pre-charge signal produced by the internal write command signal and internal pre-charge signal producing means to a memory cell array as an internal pre-charge command signal to test an operational performance of the memory cell array according to a write recovery time-period which is determined from the internal pre-charge command signal and the internal write command signal produced by the internal write command signal and internal pre-charge signal producing means and is equal to ½N of the pulse repetition period of the external clock signal.