Fault-tolerant maintenance bus architecture

A maintenance bus architecture for a fault-tolerant computer system having a plurality of circuit board assemblies and maintenance bus-compatible subsystem components thereon comprising:

• a first parent maintenance bus and a second parent maintenance bus interconnecting to each of the plurality of circuit board assemblies;
• a command module interconnected with each of the first parent maintenance bus and the second parent maintenance bus, the command module being constructed and arranged to transmit and receive control and monitor data over the first parent maintenance bus and the second parent maintenance bus in a predetermined format;
• a first bridge and a second bridge associated with each of the plurality of circuit boards;
• each first bridge being interconnected with the first parent maintenance bus and each second bridge being connected with the second parent maintenance bus;
• a child maintenance bus interconnected between the first bridge and the second bridge, the child maintenance bus being interconnected to predetermined ports on each of the maintenance bus-compatible subsystem components;
• and
• wherein each of the first bridge and the second bridge are constructed and arranged to transfer the control and monitor data addressed thereto between the child maintenance bus, the first parent maintenance bus, and the second parent maintenance bus, respectively, only one of the first bridge and the second bridge being active to transfer the control and monitor data at a given time, the first bridge and the second bridge including reset and power connections therebetween and the command module is constructed and arranged to transmit reset and power signals directly to each of the first bridge and the second bridge to thereby control power and reset of components on the respective one of the board assemblies.

A method for enabling a plurality of circuit board assemblies to monitor and control maintenance bus-compatible subsystem components in a fault-tolerant computer having a redundant maintenance bus architecture, the method comprising the steps of:

• (a) connecting a first parent maintenance bus and a second parent maintenance bus to each of a plurality of circuit board assemblies;
• (b) connecting a command module to the first parent maintenance bus and the second parent maintenance bus;
• (c) associating a first bridge and a second bridge with each one of the plurality of circuit board assemblies;
• (d) connecting each first bridge with the first parent maintenance bus and each second bridge with the second parent maintenance bus;
• (e) interconnecting a child maintenance bus between the first bridge and the second bridge;
• (f) connecting the child maintenance bus to a predetermined port on a maintenance bus-compatible subsystem component;
• (g) transmitting and receiving by the command module control and monitor data in a predetermined format over the first parent maintenance bus and the second parent maintenance bus;
• and
• (h) transferring the control and monitor data addressed to each of the first bridge and the second bridge between the child maintenance bus, the first parent maintenance bus, and the second parent maintenance bus, respectively, only one of the first bridge and the second bridge being active to transfer the control and monitor data at a given time.