System for generating N pipeline control signals by delaying at least one control signal corresponding to a subsequent data path circuit

A method for generating control signals of a pipeline device, comprising:

• generating an (n)th pipeline control signal in response to a reference clock signal;
• generating n−1 pipeline control signals in cascade from preceding pipeline control signals;
• and
• providing n pipe registers with said n pipeline control signals.

A method for generating control signals of a pipeline device, comprising:

• generating an (n)th pipeline control signal having a pulse width of wn in response to a reference clock signal;
• generating n−1 pipeline control signals in cascade from preceding pipeline control signals, wherein for i between n−1 and 1, an (i)th pipeline control signal has active regions of a pulse width w(i) generated in response to trailing edges of active regions of an (i+1)th pipeline control signal;
• and
• providing n pipe registers with said n pipeline control signals.

A pipeline device comprising:

• n data path circuits connected in cascade between an input terminal and an output terminal, said n data path circuits having transmission times (T1, . . . , Tn), wherein each transmission time is less than or equal to a period P of a reference clock signal, and at least one of said transmission times differs from another of said transmission times;
• n registers disposed at respective input terminals of said n data path circuits, wherein each register latches data passed to a corresponding one of said data path circuits;
• and
• a control signal generating circuit that produces a pipeline control signal for each of said n registers by delaying said reference clock signal by a respective delay time, the delay time of the pipeline control signal for at least one of said n registers being less than the delay time of the pipeline control signal for another of said n registers in a preceding data path circuit.