Method and system for optimizing data transfers between devices interconnected by buses operating at different clocking speeds

A system for managing data transfers between a first bus and a second bus with first and second bus clock frequencies respectively, comprising:

• a clock ratio circuit operable to determine a ratio between said first and second bus clock frequency, said first bus clock frequency clocking said first bus and said second bus clock frequency clocking said second bus;
• a clock cycle control circuit operable for receiving said first and second bus clock, said ratio between said first and second bus clock frequency and generating clock cycle control data;
• a first select circuit receiving said cycle control data, said first select circuit operable for selecting in response to said cycle control data and said first bus clock, first selected clock periods from said first bus clock, said first selected number of clock periods used with said first bus clock for data transfers between devices on said first buses;
• a second select circuit receiving said cycle control data, said second select circuit operable for selecting in response to said cycle control data and said first bus clock, second selected clock periods from said first bus clock, said second selected clock periods used with said first bus clock for data transfers between said first bus and said second bus;
• and
• an enable circuit coupled to said clock ratio circuit and operable for receiving transaction reset signals and enabling said clock ratio circuit, said clock cycle control circuit, and said first and second logic state machines.

A data processing system, comprising:

• a central processing unit (CPU);
• shared random access memory (RAM);
• read only memory (ROM);
• an I/O adapter,
• a display adapter;
• a display;
• and
• a bus system coupling devices internal to said CPU and devices external to said CPU, said bus system comprising bridging devices between buses operating at different frequencies, said bridging devices used to manage data transfers between said buses operating at different frequencies, said bridging device comprising:
• a clock ratio circuit operable to determine a ratio between said first and second bus clock frequency, said first bus clock frequency clocking said first bus and said second bus clock frequency clocking said second bus;
• a clock cycle control circuit operable for receiving said first and second bus clock, said ratio between said first and second bus clock frequency and generating clock cycle control data,
• a first select circuit receiving said cycle control data, said first select circuit operable for selecting in response to said cycle control data and said first bus clock, first selected clock periods from said first bus clock, said first selected number of clock periods used with said first bus clock for data transfers between devices on said first buses;
• a second select circuit receiving said cycle control data, said second select circuit operable for selecting in response to said cycle control data and said first bus clock, second selected clock periods from said first bus clock, said second selected clock periods used with said first bus clock for data transfers between said first bus and said second bus;
• and
• an enable circuit coupled to said clock ratio circuit and operable for receiving transaction reset signals and enabling said clock ratio circuit, said clock cycle control circuit, and said first and second logic state machines.