Method and apparatus to implement the ACPI(advanced configuration and power interface) C3 state in a RDRAM based system

A method comprising:

• receiving a message to prepare a computer system to enter a high power consumption state from a lower power consumption state;
• a CPU (“central processing unit”) resuming its instruction stream;
• a MCH (“memory control hub”) relinquishing control of a DRCG (“Direct Rambus™ Clock Generator”) to halt a special memory clock for the RDRAM;
• and
• the RDRAM entering a high-memory power consumption state.

A method comprising:

• receiving a message to prepare a computer system to enter a low power consumption state from a higher power consumption state;
• a CPU (“Central Processing Unit”) disabling an ICH (“Input/Output Control Hub”) arbiter and reading a level 3 register;
• the ICH asserting a stop clock signal to halt the CPU instruction stream;
• the CPU performing a stop grant cycle by issuing a stop grant signal to a MCH (“Memory Control Hub”);
• the MCH forwarding the stop grant signal to the ICH to trigger a C2 state;
• the ICH returning a message to the MCH, the message indicating to prepare to go to a C3 state;
• the MCH:
• emptying internal queues;
• flushing buffers;
• disabling an AGP (“Advanced Graphics Processor”) arbiter;
• issuing a self-refresh command and a current calibration command to memory banks of a RDRAM (“Rambus™ Direct Random Access Memory”);
• setting the RDRAM to a standby state;
• and
• broadcasting a power down command over a channel;
• the RDRAM entering a self-refresh and power down state;
• a RAC (“Rambus™ ASIC cell”) entering a nap mode to refresh a DLL (“Dynamic Link Library”) of the RAC;
• the MCH sending an acknowledge message to the ICH indicating to transition to the low power consumption state;
• the ICH asserting a stop CPU signal to reduce CPU power;
• and
• the MCH asserting a STOPB signal to control a DRCG (“Direct Rambus™ Clock Generator”), the DRCG generating a special memory clock for the RDRAM.

A method comprising:

• receiving a message to prepare a computer system to enter a high power consumption state from a lower power consumption state;
• an ICH (“Input/Output Control Hub”):
• deasserting a stop CPU signal;
• sending a message to a MCH (“Memory Control Hub”) to request transition to the high power consumption state;
• the MCH deasserting a STOPB signal to relinquish control of a DRCG (“Direct Rambus™ Clock Generator”);
• a RAC (“Rambus™ ASIC cell”) transitioning from a nap mode to an active mode;
• a RDRAM (“Rambus™ Direct Random Access Memory”) transitioning from a power down state to one of an active state and a standby state;
• the MCH:
• issuing temperature and current calibration commands;
• refreshing memory banks of the RDRAM;
• and
• resuming an AGP (“Advanced Graphics Processor”) arbiter;
• and
• the ICH deasserting a stop clock signal.

A computer system comprising:

• a clock synthesizer to:
• provide a first clock signal to a CPU (“central processing unit”) when the computer system is in an active state, and suspend the first clock signal when the computer system is in a clock stop state;
• provide a second clock signal to a MCH (“memory control hub”) when the computer system is in an active state, and suspend the second clock signal when the computer system is in a clock stop state;
• and
• provide a third clock signal to a high-performance RAM (“random access memory”) when the computer system is in an active state, and suspend the third clock signal when the computer system is in a clock stop state;
• the CPU coupled to the clock synthesizer to operate in response to receiving the first clock signal, and to shut down when the first clock signal is not received;
• the MCH coupled to the CPU and to the clock synthesizer to operate in response to receiving the second clock signal, and to shut down when the second clock signal is not received;
• and
• the high-performance RAM coupled to the MCH and to the clock synthesizer to operate in response to receiving the third clock signal, and to shut down when the third clock signal is not received.