Apparatus and method for controlling link stack corruption during speculative instruction branching using multiple stacks
AssigneeInternational Business Machines Corporation
InventorBalaram Sinharoy
Life of this patent
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Abstract
Instruction branching circuitry including a plurality of logical stacks each having a plurality of entries for storing an address to a corresponding instruction in memory. A counter generates a pointer to an entry in an active one of the logical stacks, the counter including incrementation logic incrementing a stored pointer value following a Push operation and decrementation logic decrementing the stored pointer value following a Pop operation to the active one of the logical stacks. Selector circuitry selects the active one of the logical stacks in accordance with the performance of the Push and Pop operations.
Claims19
Instruction branching circuitry comprising:
- (a) a plurality of logical stacks each having a plurality of entries for storing an address to a corresponding instruction in memory;
- (b) a counter for generating a pointer to an entry of an active one of the logical stacks, the counter including incrementation logic incrementing a stored pointer value following a Push operation and decrementation logic decrementing the stored pointer value following a Pop operation to the active one of the logical stacks;
- (c) circuitry for tracking, stack operations wherein said circuitry determines a current stack operation comprises a Push operation and an immediately preceding stack operation comprises a Pop operation;
- (d) selector circuitry for selecting an active one of the logical stacks, wherein the selector circuitry changes the active stack from a first stack to a second stack in response to the determination by the circuitry in (c);
- and
- (e) stack operation circuitry for performing the Pop operation to the first stack and the Push operation to the second stack after the second stack has been selected as the active stack.
A processor having integrated branch instruction processing circuitry comprising:
- (a) a register file maintaining plurality of logical stacks;
- (b) a first counter for selectively generating a pointer to a first said stack, said first counter activated in response to a first state of a control bit and incrementing with a Push into said first stack and decrementing with a Pop from said first stack;
- (c) a second counter for selectively generating a pointer to a second said stack, said second counter activated in response to a second state of said control bit and incrementing with a Push into said second stack and decrementing with a Pop from said second stack;
- (d) circuitry for tracking stack operations, wherein said circuitry determines a current stack operation comprises a Push operation and an immediately preceding stack comprises a Pop operation;
- (e) selector circuitry operable for changing said state of said control bit, and for activating a selected one of the first and second counters and corresponding first and second stacks in response to the determination by the circuitry in (d);
- (f) stack operation circuitry for performing the Pop operation to the first stack and the Push operation to the second stack after the second stack has been selected as the active stack;
- and
- (g) a branch information queue for storing said pointers to said first and second stacks and said control bit.
A method for speculative branch processing comprising:
- (a) storing an address to a corresponding instruction in memory in a selected one of a plurality of entries in a selected one of a plurality of logical stacks;
- (b) determining a current stack operation comprises a Push operation and an immediately preceding stack operation comprises a Pop operation;
- (c) selecting an active one of the plurality of logical stacks in response to the determination in step (b);
- (d) performing the Pop operation to the first stack and the Push operation to the second stack after the second stack has been selected as the active stack;
- (e) incrementing a counter corresponding to a pointer to an entry, in the active one of the plurality of logical stacks following a Push type operation;
- (f) decrementing the counter following a Pop type operation from the active one of the plurality of logical stacks;
- and
- (g) retrieving pointers to the active and inactive stacks from a queue during a branch misprediction.
Dependencies are inferred from the claim text.