Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointer

A method of allocating registers in a speculative processor comprising the steps of:

• receiving an instruction specifying a logical register for storing an execution result;
• allocating a physical register for storing the instruction, said physical register being one of a plurality of registers to store architectural data and speculative data, each physical register to store one of architectural data and speculative data;
• storing in a history buffer information identifying physical registers in an allocated sequence;
• and
• moving a retirement pointer associated with the history buffer to identify whether an execution result stored in the physical register in the allocated sequence is architectural data.

An apparatus for allowing a processor to recover from a failure of a predicted path of instructions comprising:

• a plurality of physical registers to store architectural data and speculative data, each physical register to store one of architectural data and speculative data;
• a primary array storing a mapping from logical registers to physical registers, the primary array storing a current speculative state of the processor;
• an allocator allocating an available physical register as the physical destination for storing the execution results of an instruction, the allocated physical register corresponding to a logical register;
• a history buffer coupled to the secondary array and storing information related to historical remapping of logical registers from previous physical registers to current physical registers;
• a secondary array coupled to the primary array and the history buffer, the secondary array storing a secondary speculative state of the processor including a mapping from logical registers to physical registers, the secondary array being movable to any instruction between the point of physical register allocation and retirement based on the history buffer, the secondary array being movable to any location or instruction independent of which instructions have been executed;
• wherein the secondary array can be copied to the primary array to allow the processor to recover from the failure in the predicted path.

An apparatus for allowing a processor to recover from a failure of a predicted path of instructions comprising:

• a plurality of physical registers to store architectural data and speculative data, each physical register to store one of architectural data and speculative data;
• a primary array storing a first speculative state of the processor including a mapping from logical registers to physical registers,
• a secondary array coupled to the primary array, the secondary array storing a second speculative state including a mapping from logical registers to physical registers, the second speculative state of the processor being previous to the primary speculative state of the processor;
• and
• a history buffer coupled to the secondary array and storing information related to historical remapping of logical registers from previous physical registers to current physical registers.

An apparatus comprising:

• a plurality of registers to store architecturally committed data and speculative data, each one of said plurality of registers to store one of architecturally committed data and speculative data;
• logic to store a plurality of states including a speculative state and at least one shadow state, each of said plurality of states including mappings from logical registers to physical registers in said plurality of registers;
• a history buffer storing information identifying physical registers in a mapped sequence and information related to historical remapping of logical registers from previous physical registers to current physical registers;
• and
• logic to change a retirement pointer associated with the history buffer, the retirement pointer to identify which physical pointers in the mapped sequence store architecturally committed data.

An apparatus comprising:

• a plurality of physical registers to store architecturally committed data and speculative data, each one of said plurality of registers to store one of architecturally committed data and speculative data;
• a primary array to store a speculative state of a processor including a mapping from logical registers to physical registers;
• a history buffer to store information related to historical remapping of logical registers from previous physical registers to current physical registers in a mapped sequence;
• and
• a pointer controlled by logic so as to identify a location within the history buffer, the location to identify which physical registers in the mapped sequence store architectural data.