Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions

An apparatus, comprising:

• check logic coupled to receive an instruction data block including a first variable-length instruction, wherein the check logic is configured to produce a control signal dependent upon whether or not the instruction data block includes only a portion of a second variable-length instruction;
• routing logic coupled to receive the instruction data block and configured to produce a first portion of the instruction data block and a second portion of the instruction data block;
• caching logic comprising a storage unit and coupled to receive the second portion of the instruction data block and the control signal during a time period, wherein the caching logic is configured to store the second portion of the instruction data block within the storage unit during the time period dependent upon the control signal, and wherein the caching logic is configured to produce an output, wherein during the time period the output is either the second portion of the instruction data block or the contents of the storage unit;
• and
• instruction decompression logic coupled to receive the first portion of the instruction data block, the output of the caching logic, and the control signal during the time period, wherein the instruction decompression logic is configured to produce a fixed-length instruction during the time period dependent upon the first portion of the instruction data block, the output of the caching logic, and the control signal.

A method for translating variable-length instructions to fixed-length instructions, comprising:

• receiving an instruction data block including a first variable-length instruction;
• performing the following steps simultaneously:
• translating the first variable-length instruction to produce a fixed-length instruction;
• and
• if the instruction data block includes only a portion of a second variable-length instruction, saving at least a part of the portion of the second variable-length instruction for use in subsequent translating of the second variable-length instruction.

A central processing unit, comprising:

• an instruction decompressor, comprising:
• instruction decompression logic coupled to receive a first portion of an instruction data block, an output signal, and a control signal during a time period, wherein the instruction data block includes a first variable-length instruction, and wherein the instruction decompression logic is configured to produce a fixed-length instruction during the time period dependent upon the first portion of the instruction data block, the output signal, and the control signal;
• caching logic comprising a storage unit and coupled to receive a second portion of the instruction data block and the control signal during the time period, and wherein the caching logic is configured to store the second portion of the instruction data block within the storage unit during the time period dependent upon the control signal, and wherein the caching logic is configured to produce the output signal, wherein during the time period the output signal is either the second portion of the instruction data block or the contents of the storage unit;
• and
• a processor core coupled to receive the fixed-length instruction produced by the instruction decompression logic and configured to execute the fixed-length instruction.

A computer system, comprising:

• a central processing unit, comprising:
• an instruction decompressor, comprising:
• instruction decompression logic coupled to receive a first portion of an instruction data block, an output signal, and a control signal during a time period, wherein the instruction data block includes a first variable-length instruction, and wherein the instruction decompression logic is configured to produce a fixed-length instruction during the time period dependent upon the first portion of the instruction data block, the output signal, and the control signal;
• caching logic comprising a storage unit and coupled to receive a second portion of the instruction data block and the control signal during the time period, and wherein the caching logic is configured to store the second portion of the instruction data block within the storage unit during the time period dependent upon the control signal, and wherein the caching logic is configured to produce the output signal, wherein during the time period the output signal is either the second portion of the instruction data block or the contents of the storage unit;
• and
• a processor core coupled to receive the fixed-length instruction produced by the instruction decompression logic and configured to execute the fixed-length instruction.