Coherent translation look-aside buffer
AssigneeHewlett-Packard Development Company, L.P.
InventorSamuel H. Duncan
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AssigneeHewlett-Packard Development Company, L.P.
InventorSamuel H. Duncan
Estimating the term…
The invention is a coherent translation look-aside buffer (TLB) for use in an input/output (I/O) bridge of a symmetrical multiprocessing (SMP) system. The contents of the TLBs may be kept in one of two possible states: exclusive or invalid. When the I/O bridge receives a TLB entry for storage in its TLB, the state of that entry is exclusive. Specifically, the TLB is considered the exclusive owner of the respective TLB entry. The exclusively owned TLB entry may be used by the TLB to translate I/O addresses to system addresses. If some other agent or entity of the SMP system seeks access to the TLB entry (e.g., for purposes of executing a read or write operation), the TLB is notified and the state of the TLB entry transitions to invalid. With the TLB entry in the invalid state, the TLB can no longer use the TLB entry for translating I/O addresses to system addresses.
A method for ensuring coherency of address translation information stored in a translation look-aside buffer (TLB) disposed in a first input/output (I/O) bridge of a multiprocessor computer system comprising a plurality of interconnected processors, and one or more shared memories coupled to the processors, the method comprising the steps of:
An input/output bridge for use in a distributed shared memory computer system comprising a plurality of interconnected processors, one or more shared memories that are coupled to the processors and are configured into a plurality of blocks, and one or more directories for maintaining coherency status over information in the shared memories, wherein each memory block has a corresponding system address, the I/O bridge configured to provide one or more I/O devices with access to information in the shared memories, the I/O devices using I/O addresses, the I/O bridge comprising:
The method of claim I further comprising the steps of:
An input/output (I/O) bridge for use in a computer system having one or more processors, one or more shared memories that are accessible to the one or more processors, the one or more shared memories storing address translation information, and one or more directories for maintaining coherency status over information in the shared memories, the I/O bridge comprising:
Dependencies are inferred from the claim text.