FIFO memory having reduced scale
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorMasayuki Koyama
Life of this patent
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Abstract
FIFO type memory is provided on a small circuit scale. Reading of data Dout<3:0> from a two-port type RAM (101) is executed with respect to the address specified by a read address (21) in synchronization with the fall of a clock (CLK) provided to a clock end (CLR). Writing of data Din<3:0> on the RAM (101) is executed with respect to the address specified by a write address (22) in synchronization with the rise of a clock (CLK) provided to a clock end (CLW). In an address delayer (103) after a read address (21) taking an address value is outputted, a write address (22) taking the same address value is always outputted with a fixed delay, so that a memory (100) performs the FIFO type data input/output as a whole.
Claims20
A FIFO type memory outputting data in a same order as receiving the data, comprising:
- a read address generator configured to generate a read address in synchronism with a clock signal applied to a clock signal input;
- an address delayor including a sequential circuit and connected to receive the read address generated by the read address generator and to provide a write address by delaying said read address in synchronism with said clock signal present on an input to the address delayor;
- and
- a storage element configured to input data in said same order to an address specified by said read address and to output data in said same order from an address specified by said write address, in synchronism with said clock signal.
A FIFO type memory outputting data in a same order as receiving the data, comprising:
- a first address generator configured to generate a first address in synchronization with a clock signal applied to a clock signal input thereof;
- a second address generator configured to receive said first address and said clock signal, said second address generator including a sequential circuit for holding said first address in response to said clock signal, said second address generator outputting the address held in said sequential circuit as a second address;
- and
- a storage element having a first address input end receiving said first address output from said first address generator, a second address input end receiving said second address output from said second address generator, a data input end receiving data to be written therein, and a data output end outputting data stored therein,
- wherein the storage element is configured to have data received at said data input end written therein in said same order in accordance with a respective one of said received addresses while outputting data from said data output end in said same order in accordance with the other respective one of said received addresses.
A FIFO type memory outputting data in a same order as receiving the data, comprising:
- a first address generator configured to generate a first address in synchronization with a clock signal applied to a clock signal input thereof;
- a second address generator configured to receive said first address and said clock signal, said second address generator including a sequential circuit for holding said first address in response to said clock signal, said second address generator outputting the address held in said sequential circuit as a second address;
- and
- a storage element having a first address input end receiving said first address output from said first address generator, a second address input end receiving said second address output from said second address generator, a data input end receiving data to be written therein, and a data output end outputting data stored therein,
- wherein the first address generator is capable of generating first to n-th values sequentially as the first address and repeating a generation of the first to n-th values in the same sequence with the first value following the n-th value.
Dependencies are inferred from the claim text.