Memory controller with 1×/M× read capability

A method of receiving data into a memory controller, comprising:

• a) receiving data bits which are presented to a data pad of said memory controller into respective ones of P storage elements (P≧2), in response to a count of strobe edges received at a strobe pad of said memory controller;
• b) outputting data stored in said P storage elements to a number of deskew multiplexers;
• and
• c) generating control signals for said deskew multiplexers in a clock domain of said memory controller.

A computer system, comprising:

• a) a CPU;
• c) a memory controller coupled to said CPU;
• d) an I/O controller coupled to said CPU;
• e) a number of I/O devices coupled to said I/O controller;
• and
• f) a number of memory modules coupled to said memory controller;
• wherein said memory controller comprises a plurality of data and strobe pads to which are coupled receiver circuitry for receiving data and strobe signals from said memory modules;
• and
• wherein said receiver circuitry comprises, for corresponding data and strobe pads:
• i) P storage elements coupled to receive data from said data pad (P>2), said P storage elements being controlled by respective values of a count;
• ii) a counter, said counter updating said count in response to strobe edges of strobe signals received at said strobe pad;
• and
• iii) a deskew multiplexing stage, said deskew multiplexing stage receiving data from said P storage elements, and said deskew multiplexing stage receiving control signals which are generated in a clock domain of said memory controller receiver circuitry.