Multiprocessor computer system and method for maintaining cache coherence utilizing a multi-dimensional cache coherence directory structure

A method of maintaining cache coherency across a computer system having a plurality of processor nodes, including a first processor node and a second processor node, wherein each of the plurality of processor nodes includes a cache, the method comprising:

• assigning a processor number to each of the plurality of processor nodes;
• defining a plurality of bit vectors, wherein each processor node is represented by a bit in each of the plurality of bit vectors;
• determining a first location in memory;
• reading a line from the first location in memory into the cache of said first processor node, wherein reading includes setting a bit in each of the plurality of bit vectors as a function of the processor number assigned to the first processor node;
• reading a line from the first location into the cache of said second processor node, wherein reading a line from the first location in memory into the cache of said second processor node includes setting a bit in each of the plurality of bit vectors as a function of the processor number assigned to the second processor node;
• and
• writing a line to said first location in memory, wherein writing a line includes:
• a) determining, as a function of bits set in the bit vectors, processor nodes holding a copy of the line;
• and
• b) sending a message to the processor nodes determined in step a) indicating that the line read from the first location in memory is no longer valid.

A method of maintaining cache coherency across a computer system having a plurality of processors, including a first processor and a second processor, wherein each of the plurality of processors includes a cache, the method comprising:

• assigning a processor number to each of the plurality of processors;
• defining a plurality of bit vectors, wherein each processor is represented by a bit in each of the plurality of bit vectors;
• determining a first location in memory;
• reading a line from the first location in memory into the cache of the first processor, wherein reading includes the step of setting a bit in each of the plurality of bit vectors as a function of the processor number assigned to the first processor;
• reading a line from the first location in memory into the cache of the second processor, wherein reading from the first location into the cache of the second processor includes setting a bit in each of the plurality of bit vectors as a function of the processor number assigned to the second processor;
• and
• writing to the first location in memory, wherein writing a line includes the steps of:
• a) determining, as a function of bits set in the bit vectors, processors holding a copy of the line;
• and
• b) sending a message to the processors determined in step a) indicating that the line read from the first location in memory is no longer valid.

A computer readable medium having program code for maintaining cache coherency across a computer system having a plurality of processor nodes, including a first processor node and a second processor node, wherein each of the plurality of processor nodes has an assigned processor number and wherein each of the plurality of processor nodes includes a processor and a cache, the program code comprising:

• program code for defining a plurality of bit vectors, wherein each processor node is represented by a bit in each of the plurality of bit vectors;
• program code for determining a first location in memory;
• program code for reading a line from the first location into the cache of said first processor node, wherein reading a line from the first location into the cache of said first processor node includes setting a bit in each of the plurality of bit vectors as a function of the processor number assigned to the first processor node;
• program code for reading a line from the first location into the cache of said second processor node, wherein reading a line from the first location into the cache of said second processor node includes setting a bit in each of the plurality of bit vectors as a function of the processor number assigned to the second processor node;
• and
• program code for writing a line to said first location in memory, wherein the program code for writing includes:
• a) program code for determining, as a function of bits set in the bit vectors, processor nodes holding a copy of the line;
• and
• b) program code for sending a message to the processor nodes determined in step a) indicating that the line read from the first location in memory is no longer valid.