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US 6,633,950 B1Granted
Nonvolatile writeable memory with preemption pin
AssigneeIntel Corporation
InventorsCharles W. Brown, Peter K. Hazen
Life of this patent
Estimating the term…
Abstract
A method and apparatus for preempting an operation in a nonvolatile writeable memory is performed using a pin. Preempting an operation is accomplished by either suspending the operation or by aborting the operation. Once an operation is suspended in the nonvolatile writeable memory, other operations can then be performed. Subsequently the suspended operation may be resumed.
Claims12
A nonvolatile memory, comprising:
- erase suspend circuitry connected to a memory array;
- a preemption pin connected to the erase suspense circuitry;
- and
- a command register connected to the erase suspend circuitry, wherein the erase suspend circuitry suspends an erase cycle of the memory array based on a preemption signal received from the preemption pin or the command register.
1 more element
A nonvolatile memory comprising:
- a command register that receives a preemption command to preempt an operation being performed by the nonvolatile memory;
- a preemption pin that receives a preemption signal to preempt the operation being performed by the nonvolatile memory without using a command so that the operation is suspended;
- and
- a memory control circuitry that preempts the operation being performed by the nonvolatile memory in response to a signal received from either the command register or the preemption pin.
1 more element
A method of preempting an operation being performed by a nonvolatile memory, comprising:
- receiving a preemption signal on a preemption pin or from a command register;
- and
- preempting an operation being performed by the nonvolatile memory in response to the preemption signal received from either the preemption pin, or the command register.
Dependencies are inferred from the claim text.