Stackable dual mode (registered/unbuffered) memory interface cost reduction

A method for interfacing a first memory module and a second memory module with a microprocessor, comprising:

• switching between unbuffered and registered/buffered mode for the first memory module, wherein the first memory module comprises a bus switch and a register/buffer, and wherein the switching comprises:
• detecting a type of the first memory module connected;
• and
• enabling one of the bus switch and register/buffer based on the type of memory module detected;
• interfacing the second memory module with the first memory module;
• and
• switching between unbuffered and registered/buffered mode for the second memory module.

A stackable dual mode memory interface comprising:

• means for switching between unbuffered registered/buffered modes for a first memory module, wherein the first memory module comprises a bus switch and a register/buffer, and wherein the means for switching comprises:
• means for detecting a type of the first memory module connected;
• and
• means for enabling one of the bus switch and register/buffer based on the type of memory module detected;
• means for interfacing a second memory module with the first memory module;
• and
• means for switching between unbuffered and registered/buffered modes for the second memory module.

A system for using registered/buffered and unbuffered memory comprising:

• a processor;
• a first memory module;
• an interface configured to receive a first memory module and operatively couple the first memory module to the processor;
• a second memory module,
• wherein the first memory module comprises
• a first control circuit for switching between unbuffered and registered/buffered modes,
• a system controller for detecting a type of memory module connected to the stackable dual mode memory interface and enabling one of a bus switch and a register/buffer of the first control circuit based on a type of memory module detected;
• an interface configured to receive the second memory module;
• and
• a second control circuit for switching the second memory module between unbuffered and registered/buffered modes.

An apparatus for interfacing two memory modules comprising:

• a processor;
• a first memory module;
• an interface configured to receive a first memory module and operatively couple the first memory module to the processor;
• a second memory module,
• wherein the first memory module comprises
• memory;
• connected in series with the interface configured to receive the first memory module, a first bus switch for selectively connecting the processor and the memory in an unbuffered mode;
• connected in parallel with the first bus switch and in series with the interface configured to receive the first memory module, a first register/buffer for selectively connecting the processor and the memory in a registered/buffered mode;
• operatively coupled to the first bus switch and the first register/buffer, enable/disable pins configured so that only one of the first bus switch and the first register/buffer is active at a time;
• an interface configured to receive the second memory module;
• connected in series with the interface configured to receive the second memory module, a second bus switch for selectively connecting the second memory module to the processor in an unbuffered mode;
• connected in parallel with the second bus switch and in series with the interface configured to receive the second memory module, a second register/buffer for selectively connecting the second memory module to the processor in a registered/buffered mode;
• operatively coupled to the second bus switch and the second register/buffer, enable/disable pins configured so that only one of the second bus switch and the second register/buffer is active at a time.

A computer comprising:

• an interface configured to receive a first memory module;
• a first control circuit for switching between unbuffered and registered/buffered modes, wherein the first control circuit comprises:
• a bus switch;
• and
• a register/buffer operatively coupled to the bus switch;
• a system controller for detecting a type of memory module connected to the stackable dual mode memory interface and enabling one of the bus switch and register/buffer based on the type of memory module detected,
• an interface configured to receive a second memory module;
• and
• a second control circuit for switching the second memory module between unbuffered and registered/buffered modes.