Fully connected cache coherent multiprocessing systems
AssigneeConexant Systems, Inc.
InventorsDaniel Fu, Carlton T. Amdahl, Walstein Bennett Smith, III
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Abstract
Fully connected multiple FCU-based architectures reduce requirements for Tag SRAM size and memory read latencies. A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A high-speed point-to-point Channel couples command initiators and memory with the switch matrix and with I/O subsystems.
Claims10
A multi-processor shared memory system comprising:
- a first set of point-to-point connections;
- a first set of processors each coupled to one of the first set of point-to-point connections;
- a first memory coupled to one of the first set of point-to-point connections;
- a first flow control unit including a first data switch coupled to the first set of point-to-point connections wherein the first data switch is configured to interconnect the first set of point-to-point connections to provide first data paths between the first memory and the first set of processors;
- a second set of point-to-point connections;
- a second set of processors each coupled to one of the second set of point-to-point connections;
- a second memory coupled to one of the second set of point-to-point connections;
- a second flow control unit including a second data switch coupled to the second set of point-to-point connections wherein the second data switch is configured to interconnect the second set of point-to-point connections to provide second data paths between the second memory and the second set of processors;
- and
- a third point-to-point connection coupled to the first data switch and to the second data switch wherein the first data switch is configured to interconnect the first set of point-to-point connections to the third point-to-point connection and the second data switch is configured to interconnect the second set of point-to-point connections to the third point-to-point connection to provide third data paths between the second memory and the first set of processors and between the first memory and the second set of processors.
A method of operating a multi-processor shared memory system comprising a first set of point-to-point connections, a first set of processors each coupled to one of the first set of point-to-point connections, a first memory coupled to one of the first set of point-to-point connections, a first flow control unit including a first data switch coupled to the first set of point-to-point connections, a second set of point-to-point connections, a second set of processors each coupled to one of the second set of point-to-point connections, a second memory coupled to one of the second set of point-to-point connections, a second flow control unit including a second data switch coupled to the second set of point-to-point connections, and a third point-to-point connection coupled to the first data switch and to the second data switch, the method comprising:
- interconnecting the first set of point-to-point connections in the first data switch to provide first data paths between the first memory and the first set of processors;
- interconnecting the second set of point-to-point connections in the second data switch to provide second data paths between the second memory and the second set of processors;
- and
- interconnecting the first set of point-to-point connections to the third point-to-point connection in the first data switch and interconnecting the second set of point-to-point connections to the third point-to-point connection in the second data switch to provide third data paths between the second memory and the first set of processors and between the first memory and the second set of processors.
Dependencies are inferred from the claim text.