AHB segmentation bridge between busses having different native data widths
AssigneeLSI Logic Corporation
InventorsJeffrey J. Holm, Steven M. Emerson, Matthew D. Kirkwood
Life of this patent
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Abstract
A bus bridge generally comprising a first interface, a second interface, a plurality of registers and a controller. The first interface may be connectable to a first bus having a first data width. The second interface may be connectable to a second bus having a second data width narrower than the first data width. The plurality of registers may be configured to buffer (i) data, (ii) an address, and (iii) a plurality of control signals between the first bus and the second bus. The controller configured to control the registers.
Claims20
A bus bridge comprising:
- a first interface connectable top a first bus having a first data width;
- a second interface connectable to a second bus having a second data width narrower than said first data width;
- a plurality of registers configured to buffer (i) data, (ii) an address, and (iii) a plurality of control signals between said first bus and said second bus;
- and
- a controller configured to control said registers, wherein said first interface, said second interface, said registers and said controller are on a same chip with said first bus and said second bus.
A method of bridging between a first interface connectable to a first bus and a second interface connectable to a second bus, the method comprising the steps of:
- (A) buffering data between said first interface and said second interface where said second interface has a second data width narrower than a first data width of said first interface;
- (B) buffering an address between said first interface and said second interface;
- (C) buffering a plurality of control signals between said first interface and said second interface;
- (D) controlling said buffering of said data, said address, and said control signals in response to said control signals;
- and
- (E) converting and endianess for said data between said first bus and said second bus.
A bus bridge comprising:
- a first interface connectable to a first bus having a first data width;
- a second interface connectable to a second bus having a second data width narrower than said first data width;
- a plurality of registers configured to buffer (i) data, (ii) an address, an (iii) a plurality of control signals between said first bus and said second bus;
- a controller configured to control said registers, wherein said first interface, said second interface, said registers and said controller are on a same chip with said first bus and said second bus;
- and
- a first multiplexer configured to multiplex a first and a second portions of said data buffered by said registers for presentation from said second interface.
Dependencies are inferred from the claim text.