US 6,633,940 B1 · Method and apparatus for processing interrupts in a computing system

Abstract

A method and apparatus for processing interrupts in a computing system include processing for ordering a plurality of interrupts for at least one processor. Such interrupts include system event interrupts, external device interrupts, and may further include power management interrupts, interprocessor interrupts, and/or intraprocessor interrupts. Such processing continues by generating an interrupt enable/disable signal based on the current context of a corresponding processor such that when the processor is performing a particular task which should not be interrupted, an interrupt signal is prevented from being provided to the processor. The processing also includes generating masking information to provide enable/disable masking information regarding each of the plurality of interrupts. As such, the computing system may enable/disable on a per interrupt basis the processing of a given interrupt. Such selectability in the processing of interrupts on an individual basis or global basis may be processed dynamically thereby providing greater flexibility and efficiency in interrupt processing.

Claims40

Dependent claims

A computing system having interrupt processing, the computing system comprises:

a processor operable to process an interrupt of a plurality of interrupts when an interrupt enable/disable signal is enabled, wherein the plurality of interrupts includes system event interrupts and external device interrupts;
an operating system module operably coupled to the processor, wherein the operating system module generates masking information for the processor and generates the interrupt enable/disable signal, based on a current context of the processor, said context being determined by a task being performed by said processor, wherein the masking information provides enable/disable masking information for each of the plurality of interrupts that is determined according to said context;
and
an interrupt gating module operably coupled to the processor and the operating system module, wherein the interrupt gating module registers a triggering of the interrupt and provides the interrupt to the processor when the corresponding enable/disable masking information is enabled and the interrupt enable/disable signal is enabled, and wherein the interrupt gating module overrides the interrupt based on the enable/disable signal regardless of whether the interrupt is masked via the enable/disable masking information.

1 more element

A method for interrupt processing, the method comprises the steps of:

a) generating masking information for a processor, said masking information being determined by a particular task being performed by said processor, wherein the masking information provides enable/disable masking information for each of a plurality of interrupts that should and should not be enabled based upon the particular task being performed, and wherein the plurality of interrupts includes system event interrupts and external device interrupts;
b) generating an interrupt enable/disable signal for the processor, wherein the interrupt enable/disable signal when disabled will cause the processor not to receive interrupts regardless of the enable/disable masking information;
c) registering initiation of an interrupt of the plurality of interrupts;
d) in response to the registering, providing the interrupt to the processor when corresponding enable/disable masking information of the masking information is enabled and the interrupt enable/disable signal is enabled;
and
e) processing the interrupt.

3 more elements

A computing system having interrupt processing, the computing system comprises:

a processing module;
and
memory operably coupled to the processing module, wherein the memory includes operational instructions which, when executed cause the processing module to:
(a) generate masking information for a processor of the processing module, said masking information being determined by a particular task being performed by said processor, wherein the task being performed determines interrupts that should be enabled and should not be enabled during the performance of said task, and wherein the plurality of interrupts includes system event interrupts and external device interrupts;
(b) generate an interrupt enable/disable signal for the processor, wherein the interrupt enable/disable signal when disabled will cause the processor not to receive interrupts regardless of the enable/disable masking information;
(c) register initiation of an interrupt of the plurality of interrupts;
d) in response to the registering, provide the interrupt to the processor when corresponding enable/disable masking information of the masking information is enabled and the interrupt enable/disable signal is enabled;
and e) process the interrupt.

5 more elements

Dependencies are inferred from the claim text.

Method and apparatus for processing interrupts in a computing system

Life of this patent

Method and apparatus for processing interrupts in a computing system

Life of this patent

Abstract

Claims40