US 6,633,621 B1 · Apparatus and method for synchronizing a clock using a phase-locked loop circuit

Abstract

A system for synchronizing a clock includes a phase-locked loop (PLL) circuit that generates or receives (304) timing errors that are based on timing information from multiple timing sources. Gain blocks (214) weight (306) the timing errors, which are then combined (308) into a loop time error. A loop integrator (226) integrates (310) the loop time error to produce an input used to adjust (312) an oscillator frequency. A corresponding oscillator clock signal is fed back (240) to one or more phase detectors (206), which receive (302) timing reference signals and generate timing errors. When a timing errors indicates that a problem exists with a timing source, the impact of the problematic timing source is reduced (430, 504), or oscillator frequency adjustments are suspended (608). When used on a satellite (700), at least one of the timing errors can be based on times of transmit and times of arrival of time messages exchanged between the satellite and its neighbors (716).

Claims22

Dependent claims

A method for synchronizing a clock using a phase-locked loop circuit which includes an adjustable oscillator and a feedback loop, the method comprising:

receiving multiple timing errors, wherein each timing error is based on timing information from one of multiple timing sources;
combining the multiple timing errors, resulting in a loop time error;
generating an input to the adjustable oscillator based on the loop time error, wherein the adjustable oscillator adjusts an oscillator frequency based on the input, and the oscillator frequency is fed back through the feedback loop, causing the loop time error to approach zero;
monitoring the multiple timing errors;
applying a weighting factor to each of the multiple timing errors, prior to combining the multiple timing errors;
when a particular timing error of the multiple timing errors is out of tolerance, reducing an impact of the particular timing error;
determining whether all of the multiple timing errors are out of tolerance;
and
when all of the multiple timing errors are out of tolerance, suspending oscillator frequency adjustments.

6 more elements

Dependencies are inferred from the claim text.

Apparatus and method for synchronizing a clock using a phase-locked loop circuit

Life of this patent

Apparatus and method for synchronizing a clock using a phase-locked loop circuit

Life of this patent

Abstract

Claims22