Digital circuit for formatting and compressing radar video data

A digital circuit for compressing and formatting video data from a seeker on board a missile, said digital circuit comprising:

• (a) a frame controller for receiving said video data from an external memory and a scan count and providing a frame of said video data which includes said scan count, non video data and compressed video data, said frame controller including:
• (i) a frame formatter for receiving a first clock signal, said frame formatter, responsive to said first clock signal, generating said non video data, a video enable signal, a video load signal, a video select signal, a frame sync signal and a frame strobe signal;
• (ii) a multiplexer connected to said frame formatter to receive said video select signal, said multiplexer receiving said compressed video data from said external memory and said scan count, said multiplexer passing said compressed video data through said multiplexer when said video select signal is at a first logic state and said multiplexer passing said scan count through said multiplexer when said video select signal is at a second logic state;
• (iii) a parallel to serial shift register connected to said multiplexer and said frame formatter to receive said compressed video data, said scan count and said video load signal, said parallel to serial shift register receiving said first clock signal, said parallel to serial shift, responsive to said first clock signal and said video load signal, converting said compressed video data and said scan count from a parallel data format to a serial data format;
• (iv) a first logic gate connected to said parallel to serial shift register to receive said compressed video data and said scan count, said first logic gate being connected to said frame formatter to receive said video enable signal, said first logic gate passing said non video data through said first logic gate when said video enable signal is at a first logic state and said first logic gate passing said compressed video data and said scan count through said first logic gate when said video enable signal is at a second logic state;
• (v) a second logic gate connected to said frame formatter to receive said video enable signal, said frame sync signal and said video load signal, said second logic gate processing said video enable signal, said frame sync signal and said video load signal to generate a read signal, a second clock signal, and a pair of chip select signals which allows for a transfer of said compressed video data from said external memory to said frame controller;
• (vi) an address counter connected to said second logic gate to receive said clock signal, said address counter, responsive to said clock signal, generating a first plurality of addresses to effect said transfer of said video data from said external memory to said frame controller;
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• (vii) a Flip-Flop having a data input connected to said first logic gate to receive said non video data, said compressed video data and said scan count, said Flip-Flop having a clock input for receiving said first clock signal, said Flip-Flop having said non video data, said video data and said scan count clocked through said Flip-Flop by said first clock signal providing at an output of said Flip-Flop said frame of video data which is synchronized with said first clock signal;
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• (b) a data compression circuit for receiving a plurality of scans of said video data and a master trigger signal from said seeker, said data compression circuit being connected to said frame formatter to receive said frame strobe signal, said data compression circuit receiving a third clock signal, said data compression circuit, responsive to said frame strobe signal, said master trigger signal and said third clock signal, compressing said plurality of scans of said video data into said compressed video data which includes peak value video data and average value video data;
• said data compression circuit generating a write signal and a second plurality of addresses to effect a storage of said compressed video data into said external memory allowing said frame formatter to effect said transfer of said compressed video data from said external memory to said frame controller;
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• said data compression circuit generating said scan count, said data compression circuit providing said scan count to said frame formatter.