Pulse code sequence analyzer

A pulse code analyzer for analyzing data comprising

• data converter means having a reference and an auxiliary channel for each receiving the data,
• clock means for recovering a clock signal from the data and applying generated clock signals to the data converter means,
• counter means coupled with the data converter means and clock means for recording errors occurring in the data, and
• processor means coupled to the counter, data converter and clock means for controlling the clock and data converter means to detect errors occurring in the data received by the data converter means and for recording a matrix of the recorded errors determining a probability predicting the data errors.

A pulse code analyzer for analyzing data comprising

• data converter means having a reference and an auxiliary channel for each receiving the data,
• clock means for recovering a clock signal from the data and applying generated variable time delayed subtone clock signals to the data converter reference and auxiliary channels,
• counter means coupled with the data converter reference and auxiliary channels for recording errors occurring in the data, and
• processor means coupled to the counter, data converter and clock means for controlling a time delay between the subtone clock signals and a voltage level of the received channel data to detect errors occurring in the data received by the data converter means and for recording a three dimensional matrix of the recorded errors determining a probability predicting the data errors.

A pulse code analyzer for analyzing incoming serial data comprising:

• data converter means having a reference and an auxiliary channel for each receiving the incoming serial data;
• clock means for recovering a clock signal from the incoming serial data and applying generated clock signals to the reference and auxiliary channels of the data converter means;
• counter means coupled with the data converter means and clock means for recording accumulated errors occurring in the data;
• and
• processor means coupled to the counter, data converter and clock means for controlling the clock and data converter means to detect errors occurring in the data received by the data converter means and for recording a matrix of the recorded accumulated errors and determining a probability predicting the data errors.