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US 6,633,576 B1Granted
Apparatus and method for interleaved packet storage
OwnerWilliam Melaragni, Geoffrey B. Ladwig +1inventors
InventorsWilliam Melaragni, Geoffrey B. Ladwig, Richard L. Angle
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Abstract
An apparatus and method for storage of memory packets with a high aggregate bandwidth is disclosed. An odd-even memory bank structure effectively doubles the memory available for packet storage. A packet memory arbitration scheme aligns access of devices reading and writing into packet memory allowing full-rate access to the packet memory.
Claims27
An apparatus for storing network packets, comprising:
- a latency sensitive packet handler for receiving network packets;
- a packet memory structure including a first memory bank and a second memory bank to store network packets;
- a latency insensitive packet processor connected to the first and second memory banks;
- and
- a memory controller connected to the memory banks and to the packet handler, said memory controller including an arbitration agent which delays the packet processor from accessing one of the memory banks when the packet processor is in a conflict for the same one of the memory banks with the packet handler.
2 more elements
An apparatus for storing packets in memory for processing and routing, comprising:
- means for receiving a plurality of packets having a first descriptor;
- means for preparing the packets for processing and routing;
- means for writing individual of the plurality of packets alternately into a first memory structure, and a second memory structure;
- means for alternately reading individual packets from the first memory structure and the second memory structure;
- means for processing the plurality of packets for routing;
- means for writing individual of the plurality of packets alternately into the first memory structure, and the second memory structure;
- means for alternately reading individual packets from the first memory structure and the second memory structure;
- and
- means for routing the plurality of packets to a plurality of destinations.
6 more elements
A method for storing packets in memory for processing and routing, comprising:
- receiving a plurality of packets having a first descriptor;
- preparing the packets for processing and routing;
- writing individual of the plurality of packets alternately into a first memory structure, and a second memory structure;
- alternately reading individual packets from the first memory structure and the second memory structure;
- processing the plurality of packets for routing;
- writing individual of the plurality of packets alternately into the first memory structure, and the second memory structure;
- alternately reading individual packets from the first memory structure and the second memory structure;
- and
- routing the plurality of packets to a plurality of destinations.
6 more elements
A method for arbitrating reads of packets into memory, comprising:
- providing a memory system having a first packet handler, a packet processor, a second packet handler, a packet memory connected to the first and second packet handlers and to the packet processor, and a memory controller connected to the packet memory and to the first and second packet handlers;
- performing a plurality of reads with the packet processor from a plurality of memory locations in the packet memory;
- performing a plurality of reads with the second packet manager from the plurality of packet memory locations in the packet memory;
- and
- delaying any one of the plurality of reads performed by the packet processor when the any one of the plurality reads performed by the packet processor is to a common memory location of any one of the plurality of reads performed by the second packet manager.
2 more elements
A method for arbitrating writes of packets into memory, comprising:
- providing a memory system having a first packet handler, a packet processor, a second packet handler, a packet memory connected to the first and second packet handlers and to the packet processor, and a memory controller connected to the packet memory and to the first and second packet handlers;
- performing a plurality of writes using the packet processor to a plurality of memory locations in the packet memory;
- performing a plurality of writes using the first package handler into the plurality of packet memory locations in the packet memory;
- and
- delaying any one of the plurality of writes performed by the packet processor when the any one of the plurality of writes performed by the packet processor is to a common memory location of any one of the plurality of writes performed by the first packet handler.
2 more elements
A method for arbitrating reads and writes of packets into memory, comprising:
- providing a memory system having a first packet handler, a packet processor, a second packet handler, a packet memory connected to the first and second packet handlers and to the packet processor, and a memory controller connected to the packet memory and to the first and second packet handlers;
- performing a plurality of writes using the packet processor to a first plurality of memory locations in the packet memory;
- performing a plurality of reads using the packet processor from a second plurality of memory locations in the packet memory;
- performing a plurality of writes using the first packet handler into the first plurality of packet memory locations in the packet memory;
- performing a plurality of reads using the second packet handler from the second plurality of packet memory locations in the packet memory;
- delaying any one of the plurality of writes performed by the packet processor when the any one of the plurality of writes performed by the packet processor is to a common memory location of any one of the plurality of writes performed by the first packet handler;
- delaying any one of the plurality of reads performed by the packet processor when the any one of the plurality reads performed by the packet processor is to a common memory location of any one of the plurality of reads performed by the second packet handler;
- completing the any one of the plurality of writes by the packet processor after delaying any one of the plurality of writes;
- and
- completing the any one of the plurality of reads by the packet processor after delaying any one of the plurality of reads.
7 more elements
Dependencies are inferred from the claim text.