Method and apparatus for generating massive interrupts in random access memory (RAM)
AssigneeCiena Corporation
InventorsRaanan Ben-Zur, Sandra Maria Frazier, Shi-Woang Wang
Life of this patent
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Abstract
A method and apparatus for generating massive interrupts in random access memory (RAM) are provided, comprising receiving and storing Time Slot network (TS Net) data frames comprising switching event information in a first RAM area. Compare operations are performed among prespecified ones of the TS Net data frames. Unit interrupt bits are set in a corresponding location of a second RAM area in response to detected bit differences resulting from the compare operations. Interrupt status bits are set in a corresponding location of a third RAM area in response to set unit interrupt bits. Massive interrupt signals are generated in response to set unit interrupt bit.
Claims37
A method for generating massive interrupts in random access memory (RAM), comprising:
- receiving and storing a plurality of data frames comprising switching event information in a first RAM area;
- performing compare operations among prespecified ones of the plurality of data frames;
- setting at least one unit interrupt bit in a corresponding location of a second RAM area in response to at least one detected bit difference resulting from the compare operations;
- setting at least one interrupt status bit in a corresponding location of a third RAM area in response to the set at least one unit interrupt bit;
- and
- generating a massive interrupt signal in response to at least one set unit interrupt bit.
An apparatus for generating massive interrupts in random access memory (RAM), comprising:
- at least one first RAM area, wherein a plurality of data frames comprising switching event information are received and stored;
- at least one comparator coupled to the at least one first RAM area, wherein compare operations are performed among prespecified ones of the plurality of data frames;
- at least one second RAM area coupled to the at least one comparator, wherein at least one unit interrupt bit is set in a corresponding location in response to at least one detected bit difference resulting from the compare operations;
- at least one third RAM area coupled to the at least one second RAM area, wherein at least one interrupt status bit is set in a corresponding location in response to the set at least one unit interrupt bit;
- and
- interrupt circuitry coupled among the at least one second and third RAM areas, wherein at least one massive interrupt signal is generated in response to at least one set unit interrupt bit.
An apparatus for generating massive interrupts in random access memory (RAM), comprising:
- means for receiving and storing a plurality of data frames comprising switching event information in a first RAM area;
- means for performing compare operations among prespecified ones of the plurality of data frames;
- means for setting at least one unit interrupt bit in a corresponding location of a second RAM area in response to at least one detected bit difference resulting from the compare operations;
- means for setting at least one interrupt status bit in a corresponding location of a third RAM area in response to the set at least one unit interrupt bit;
- and
- means for generating a massive interrupt signal in response to at least one set unit interrupt bit.
A computer readable medium containing executable instructions which, when executed in a processing system, cause the processing system to generate massive interrupts in random access memory (RAM), by:
- receiving and storing a plurality of data frames comprising switching event information in a first RAM area;
- performing compare operations among prespecified ones of the plurality of data frames;
- setting at least one unit interrupt bit in a corresponding location of a second RAM area in response to at least one detected bit difference resulting from the compare operations;
- setting at least one interrupt status bit in a corresponding location of a third RAM area in response to the set at least one unit interrupt bit;
- and
- generating a massive interrupt signal in response to at least one set unit interrupt bit.
An electromagnetic medium containing executable instructions which, when executed in a processing system, cause the processing system to generate massive interrupts in random access memory (RAM), by:
- receiving and storing a plurality of data frames comprising switching event information in a first RAM area;
- performing compare operations among prespecified ones of the plurality of data frames;
- setting at least one unit interrupt bit in a corresponding location of a second RAM area in response to at least one detected bit difference resulting from the compare operations;
- setting at least one interrupt status bit in a corresponding location of a third RAM area in response to the set at least one unit interrupt bit;
- and
- generating a massive interrupt signal in response to at least one set unit interrupt bit.
Dependencies are inferred from the claim text.