Partial selection of passive element memory cell sub-arrays for write operations

In a semiconductor integrated circuit having a memory array comprising a plurality of sub-arrays, a method of writing a data set into the memory array and reading the data set from the memory array, said method comprising the steps of:

• providing separately selectable groups of said sub-arrays, each group containing a plurality of sub-arrays;
• organizing the memory array to associate the data set with a predetermined plurality of sub-array groups, with a corresponding portion of the data set associated with each corresponding sub-array within the predetermined plurality of sub-array groups;
• cycling through each sub-array group of the predetermined plurality, selecting at any time one such group to simultaneously write into each sub-array of the selected group a corresponding portion of the data set, until all the predetermined plurality of groups have been selected, and the complete data set written into the predetermined plurality of sub-array groups;
• and
• selecting all of the predetermined plurality of sub-array groups to simultaneously read from each corresponding sub-array within the predetermined plurality of sub-array groups a corresponding portion of the data set, thereby reading simultaneously the data set from the memory array.

In a semiconductor integrated circuit having a programmable memory array comprising a plurality of sub-arrays, a method for reducing programming power while writing a data set into the memory array, and for preserving read bandwidth while reading the same data set from the memory array, said method comprising the steps of:

• organizing the memory array to associate the data set with a predetermined number of sub-arrays, with a corresponding portion of the data set associated with each corresponding sub-array within the predetermined number of sub-arrays;
• writing the data set by using a plurality of internal write cycles, each writing a respective portion of the data set simultaneously into the associated sub-arrays;
• and
• reading the data set using a single internal read cycle to simultaneously access all the predetermined number of sub-arrays.

In a semiconductor integrated circuit having a memory array comprising a plurality of sub-arrays, a method of writing a data set into the memory array and reading the same data set from the memory array, said method comprising the steps of:

• selecting a first group of M sub-arrays to simultaneously write data associated therewith into the first group of sub-arrays;
• selecting a second group of N sub-arrays to simultaneously write data associated therewith into the second group of sub-arrays;
• and
• selecting both the first group of M sub-arrays and the second group of N sub-arrays to read data simultaneously from both groups.