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AssigneesHitachi, Ltd., Hitachi ULSI Engineering Corp.
InventorsMasaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
Estimating the term…
Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.
A semiconductor memory device comprising:
A semiconductor memory device comprising:
A semiconductor memory device comprising:
A method of operating a semiconductor system, having at least a volatile memory including plural memory portions and enabled to operate in either a first operation mode or a second operation mode, comprising:
Dependencies are inferred from the claim text.