Antifuse detection circuit

A system comprising:

• a processor;
• and
• an integrated circuit device coupled to the processor, the integrated circuit device comprising:
• a first antifuse having a first state;
• a second antifuse having a second state:
• and
• a single pair of cross-coupled P-channel transistors coupled between the first antifuse and the second antifuse to latch the first state of the first antifuse.

A method comprising:

• selecting a circuit in a system;
• programming a selected one of a pair of antifuses to address the selected circuit;
• and
• latching a state of the pair of antifuses comprising latching a first node coupled to a first antifuse and latching a second node coupled to a second antifuse with a single pair of cross-coupled P-channel transistors.

A method of operating a memory device comprising:

• detecting a defective memory cell in a memory device;
• selecting a redundant memory cell to replace the defective memory cell;
• programming a selected one of a pair of antifuses to address the selected redundant memory cell;
• and
• latching a state of the pair of antifuses comprising latching a first node coupled to a first antifuse and latching a second node coupled to a second antifuse with a single pair of cross-coupled P-channel transistors.

An antifuse circuit comprising:

• a single pair of cross-coupled transistors comprising a first transistor comprising a first terminal coupled to a positive voltage supply, a gate, and a second terminal, and a second transistor comprising a first terminal coupled to the positive voltage supply, a gate coupled to the second terminal of the first transistor, and a second terminal coupled to the gate of the first transistor;
• a first antifuse coupled between a reference voltage and the second terminal of the first transistor, the first antifuse having a first state;
• and
• a second antifuse coupled between the reference voltage and the second terminal of the second transistor, the second antifuse having a second state, the gate of the first transistor and the gate of the second transistor to be latched to opposite states by the cross-coupled transistors determined by the first state of the first antifuse and the second state of the second antifuse.

A method of detecting an antifuse comprising:

• coupling a first plate of a first antifuse to a reference voltage, the first antifuse having a first state;
• coupling a first plate of a second antifuse to the reference voltage, the second antifuse having a second state;
• coupling a positive voltage supply to a first terminal of each of a first transistor and a second transistor, a gate of the first transistor being coupled to a second terminal of the second transistor, and a gate of the second transistor being coupled to a second terminal of the first transistor;
• and
• latching the first state of the first antifuse at a first node coupling a second plate of the first antifuse to the gate of the second transistor and latching the second state of the second antifuse at a second node coupling a second plate of the second antifuse to the gate of the first transistor.

An antifuse circuit comprising:

• a first antifuse having a first state;
• a second antifuse having a second state;
• and
• means for detecting the first state of the first antifuse and the second state of the second antifuse.

A system comprising;

• a processor;
• and
• an integrated circuit device coupled to the processor, the integrated circuit device comprising:
• a single pair of cross-coupled transistors comprising a first transistor comprising a first terminal coupled to a positive voltage supply, a gate, and a second terminal, and a second transistor comprising a first terminal coupled to the positive voltage supply, a gate coupled to the second terminal of the first transistor, and a second terminal coupled to the gate of the first transistor;
• a first antifuse coupled between a reference voltage and the second terminal of the first transistor, the first antifuse having a first state;
• and
• a second antifuse coupled between the reference voltage and the second terminal of the second transistor, the second antifuse having a second state, the gate of the first transistor and the gate of the second transistor to be latched to opposite states by the cross-coupled transistors determined by the first state of the first antifuse and the second state of the second antifuse.

A method of operating a memory device comprising:

• detecting a defective memory cell in a memory device;
• selecting a redundant memory cell to replace the defective memory cell;
• programming a selected one of a first antifuse and a second antifuse in the memory device to address the selected redundant memory cell;
• coupling a first plate of the first antifuse to a reference voltage, the first antifuse having a first state;
• coupling a first plate of the second antifuse to the reference voltage, the second antifuse having a second state;
• coupling a positive voltage supply to a first terminal of each of a first transistor and a second transistor in the memory device, a gate of the first transistor being coupled to a second terminal of the second transistor, and a gate of the second transistor being coupled to a second terminal of the first transistor;
• and
• latching the first state of the first antifuse at a first node coupling a second plate of the first antifuse to the gate of the second transistor and latching the second state of the second antifuse at a second node coupling a second plate of the second antifuse to the gate of the first transistor.