Test device for semiconductor memory circuit
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorTamaki Iwasaki
Life of this patent
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Abstract
A semiconductor device is provided with a memory, scan chains each comprising plural flip-flops, combination circuits which receive the outputs from the respective flip-flops in the scan chains, and a selector circuit which receives the outputs from the respective flip-flops and the outputs from the combinational circuits, selects test signals outputted from the flip-flops when the semiconductor device is in a test mode, and outputs the test signals to the memory, thereby to operate the memory. Therefore, stress can be reliably applied to the memory when a burn-in test is carried out.
Claims11
A semiconductor device comprising:
- a test circuit to be subjected to a test;
- plural flip-flops which are connected in a scan chain;
- and
- a selector circuit for receiving the outputs from the plural flip-flops, and the outputs from combinational circuits which receive the outputs from the plural flip-flops, selecting the outputs from the plural flip-flops as test signals when the semiconductor device is in a test mode, and outputting the test signals to the test circuit, thereby to operate the test circuit.
Dependencies are inferred from the claim text.