Processing of progressive video signals in digital TV receivers

A buffering system in a digital TV receiver for processing video signals having a plurality of formats, the buffering system comprising:

• a memory for buffering the video signals, the memory having a first buffer and a second buffer;
• means for generating a standard buffering signal in response to the reception of a video signal;
• means for processing the standard buffering signal to determine if the received video signal is in a first format or in a second format;
• means for buffering the received video signal in the memory in accordance with the standard buffering signal if the received video signal is in the first format, the first format video signal being alternately written into the first and second buffers and alternately read from the first and second buffers;
• means for partially overriding the standard buffering signal to generate a modified buffering signal if the received video signal is in a second format;
• and
• means for buffering the second format video signal in the memory in accordance with the modified buffering signal such that the second format video signal is buffered in the memory without the loss of data.

A memory management process for buffering video signals in a memory partitioned into first and second buffers, the process comprising the steps of:

• receiving a video signal;
• generating a standard buffering signal in response to reception of the video signal;
• processing the standard buffering signal to determine if the received video signal is interlaced or progressive;
• buffering the received video signal in the memory in accordance with the standard buffering signal if the received video signal is interlaced, the interlaced video signal being buffered in the memory such that the fields of the interlaced video are alternately written into the first and the second buffers and alternately read from the first and second buffers;
• partially overriding the standard buffering signal to generate a modified buffering signal if the received video signal is progressive;
• and
• buffering the received progressive video signal in the memory in response to reception of the modified buffering signal such that the progressive signal is buffered in the memory without the loss of frames of data.

A buffering system for processing interlaced and progressive video signals, the buffering system comprising:

• a memory for buffering the video signals, the memory having a first buffer and a second buffer;
• a video signal source for providing interlaced and progressive video signals to the memory and generating a memory write signal;
• a signal generator for generating a memory read signal;
• a memory controller communicatively connected to the memory, video signal source, and signal generator, the memory controller responsive to the memory write signal to cause interlaced and progressive video signals provided by the video signal source to be written into the memory such that fields of an interlaced video signal are alternately written into the first buffer and the second buffer and frames of a progressive video signal are consecutively written into either the first buffer or the second buffer, the memory controller responsive to the memory read signal to cause data to be alternately read from the first buffer and the second buffer;
• and
• a system controller communicatively connected to the memory controller, the system controller detecting when the memory controller is causing a first frame of the progressive video signal to be written into one of the first and second buffers, the system controller partially overriding the operation of the memory controller such that subsequent frames of the progressive video signal are alternately written into the first buffer and the second buffer.

A buffering system for processing interlaced and progressive video signals, the buffering system comprising:

• a memory for buffering the video signals, the memory having a first buffer and a second buffer;
• a video signal source for providing interlaced and progressive video signals to the memory and generating a memory write signal;
• a signal generator for generating a memory read signal;
• a memory controller communicatively connected to the memory, video signal source, and signal generator, the memory controller responsive to the memory write signal to cause interlaced and progressive video signals provided by the video signal source to be written into the memory such that fields of an interlaced video signal are alternately written into the first buffer and the second buffer and frames of a progressive video signal are consecutively written into either the first buffer or the second buffer, the memory controller responsive to the memory read signal to cause data to be alternately read from the first buffer and the second buffer;
• and
• a system controller communicatively connected to the memory controller, the system controller detecting when the memory controller is causing a first frame of the progressive video signal to be written into one of the first and second buffers, the system controller partially overriding the operation of the memory controller such that frames of the progressive video signal are consecutively read from either the first buffer or the second buffer.