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US 6,633,299 B1Granted
Method and apparatus for implementing smart allocation policies for a small frame buffer cache serving 3D and 2D streams
AssigneeIntel Corporation
InventorsKrishnan Sreenivas, Aditya Sreenivas, Tom Piazza
Life of this patent
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Abstract
In one embodiment, the invention is a method. The method includes monitoring a data stream. The method also includes partitioning a cache into two sub-caches based on monitoring the data stream.
Claims28
A method comprising:
- observing a data stream;
- partitioning a cache into a first portion and a second portion in response to the observing the data stream;
- maintaining the first portion;
- maintaining the second portion;
- and
- wherein maintaining the first portion includes:
- reading a set of spans into the first portion;
- writing to a span of the set of spans;
- marking a span written to as a dirty span;
- writing to a dirty span;
- and
- marking a dirty span written to as a fully dirty span.
9 more elements
A medium embodying instructions, the instructions when executed by a processor causing the processor to perform a method, the method comprising:
- observing a data stream;
- partitioning a cache into a first portion and a second portion in response to the observing the data stream;
- maintaining the first portion;
- maintaining the second portion;
- and wherein maintaining the first portion includes:
- reading a set of spans into the first portion;
- writing to a span of the set of spans;
- marking a span written to as a dirty span;
- writing to a dirty span;
- marking a dirty span written to as a fully dirty span;
- and
- scrubbing the first portion, the scrubbing including writing back and removing fully dirty spans in LRU order, the scrubbing further including writing back and removing dirty spans in LRU order.
9 more elements
A medium embodying instructions, the instructions when executed by a processor causing the processor to perform a method, the method comprising:
- observing a data stream;
- partitioning a cache into a first portion and a second portion in response to the observing the data stream;
- maintaining the first portion;
- maintaining the second portion;
- and wherein maintaining the second portion includes:
- writing to a span of the set of spans;
- marking a span written to as a dirty span;
- writing to a dirty span;
- marking a dirty span written to as a fully dirty span;
- and
- scrubbing the second portion, the scrubbing including writing back and removing fully dirty spans in LRU order, the scrubbing further including writing back and removing dirty spans in LRU order.
8 more elements
A system comprising:
- a processor;
- a control hub coupled to the processor;
- a memory coupled to the control hub;
- a graphics subsystem coupled to the control hub, the graphics subsystem having a cache, the internal structure of the cache dynamically reconfigurable into a first portion and a second portion in response to changes in a data stream received by the graphics subsystem, the first portion and the second portion maintainable independently, and wherein maintenance of the first portion includes reading a set of spans into the first portion, writing to a span of the set of spans, marking a span written to as a dirty span, writing to a dirty span, and marking a dirty span written to as a fully dirty span.
1 more element
An apparatus comprising:
- a cache suitable for coupling to a bus, the cache configurable in response to data received on the bus, the cache having a first and a second portion, the first portion configurable as independent of the second portion or unified with the second portion, the first portion expandable or collapsible within the cache, the first portion and the second portion maintainable independently, and wherein maintenance of the first portion includes reading a set of spans into the first portion, writing to a span of the set of spans, marking a span written to as a dirty span, writing to a dirty span, and marking a dirty span written to as a fully dirty span.
Dependencies are inferred from the claim text.